Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
445 words
An apparatus for multiplying two sequences of N digital numbers a i and b i , which may represent signal pulses of various amplitudes, comprising: a first plurality of t read-only memories (ROMs), having a common input adapted to receive the sequence of numbers a i , each ROM coding the numbers a i into a j ,i =a j modulo m i , with 0≦a j ,i ≦m i -1; a first plurality of t extending means, an input of each connected to an output of a read-only memory, for extending the digital signal with N-1 zero values; a first plurality of t digital-to-analog (D/A) converters, an input of each being connected to an output of a zero extender, for converting the digital quantity received from the extender into its corresponding analog value; a second plurality of t read-only memories (ROMs), having a common input adapted to receive the sequence of numbers b i , each ROM coding the numbers b i into b j ,i =b j modulo m i , with 0≦b j ,i ≦m i -1; a second plurality of t extending means, an output of each connected to an output of a read-only memory of the second plurality, for extending the digital signal with N-1 zero values; a second plurality of t digital-to-analog (D/A) converters, an input of each being connected to an output of a zero extender of the second plurality, for converting the digital quantity received from the extender into its corresponding analog value; a plurality of t means for convolving two input analog signals, one from each of the first and second D/A converters, the output of each convolving means being an analog convolved signal, approximately equal to the convolution (a j ,i) * (b j ,i) modulo m i ; a plurality of t analog-to-digital (A/D) converters, each having its input connected to the output of one of the convolvers, for converting the analog signal back to digital form; a plurality of t means for multiplying by an integer u i , each means having an input connected to an output of an A/D converter, the integer u i being defined by the relationship u i =1 mod m i and u j =0 mod m j for j≠i, where the m i represent integers and the u i represent integers pairwise relatively prime; means for summing, whose input comprise the t multiplying means; and means, whose input is connected to the output of the summing means, for reducing the output of the summing means to a value between 0≦m(=m 1 m 2 . . . m t ) -1 congruent to the output modulo m.
Claim 2
Independent Claim
445 words
An apparatus for multiplying two sequences of N digital numbers a i and b i , which may represent signal pulses of various amplitudes, comprising: a first plurality of t read-only memories (ROMs), having a common input adapted to receive the sequence of numbers a i , each ROM coding the numbers a i into a j ,i =a j modulo m i , with 0≦a j ,i ≦m i -1; a first plurality of t extending means, an input of each connected to an output of a read-only memory, for extending the digital signal with N-1 zero values; a first plurality of t digital-to-analog (D/A) converters, an input of each being connected to an output of a zero extender, for converting the digital quantity received from the extender into its corresponding analog value; a second plurality of t read-only memories (ROMs), having a common input adapted to receive the sequence of numbers b i , each ROM coding the numbers b i into b j ,i =b j modulo m i , with 0≦b j ,i ≦m i -1; a second plurality of t extending means, an output of each connected to an output of a read-only memory of the second plurality, for extending the digital signal with N-1 zero values; a second plurality of t digital-to-analog (D/A) converters, an input of each being connected to an output of a zero extender of the second plurality, for converting the digital quantity received from the extender into its corresponding analog value; a plurality of t means for convolving two input analog signals, one from each of the first and second D/A converters, the output of each convolving means being an analog convolved signal, approximately equal to the convolution (a j ,i) * (b j ,i) modulo m i ; a plurality of t analog-to-digital (A/D) converters, each having its input connected to the output of one of the convolvers, for converting the analog signal back to digital form; a plurality of t means for multiplying by an integer u i , each means having an input connected to an output of an A/D converter, the integer u i being defined by the relationship u i =1 mod m i and u j =0 mod m j for j≠i, where the m i represent integers and the u i represent integers pairwise relatively prime; means for summing, whose input comprise the t multiplying means; and means, whose input is connected to the output of the summing means, for reducing the output of the summing means to a value between 0≦m(=m 1 m 2 . . . m t ) -1 congruent to the output modulo m.
Claim 3
Dependent Claim
152 words
The apparatus according to claim 1, further comprising: a read-only memory, connected between the source of signals a i and the first plurality of t ROMs, for reducing modulo m 1 , . . . , m s , the values of the numbers a i to a sequence of integers between 0 and m 1 -1, 0 and m 2 -1, . . ., 0 and m s -1, the combination comprising an apparatus for processing a i numbers; and a read-only memory, connected between the source of signals b i and the second plurality of t ROMs, for reducing modulo m 1 , . . ., m s , the values of the numbers b i to a sequence of integers between 0 and m 1 -1, 0 and m 2 -1, . . ., 0 and m s -1, the combination comprising an apparatus for processing b i numbers.
Claim 4
Dependent Claim
152 words
The combination according to claim 2, further comprising: a plurality of s-1 apparatuses for processing a i numbers, connected in parallel with the first-named apparatus for processing a i numbers; a plurality of s-1 apparatuses for processing b i numbers, connected in parallel with the first-named apparatus for processing b i numbers; the apparatus for multiplying two sequences of numbers further comprising: another plurality of s means for multiplying each of whose inputs comprises an output from a means for reducing the output of the first signal summer; a second means for summing, whose input comprises the s means for multiplying, for summing the outputs of the multipliers; and a second means, whose input is connected to the output of the second summing means, for reducing the output of the second summing means to a value between 0≦m(=m 1 m 2 . . . m t )-1 congruent to it modulo m.
Claim 5
Dependent Claim
14 words
The combination according to claim 1, wherein: the means for convolving comprises charge-coupled devices.
Claim 6
Dependent Claim
15 words
The combination according to claim 4 wherein: the means for multiplying comprise charge coupled devices.
Claim 7
Dependent Claim
16 words
The combination according to claim 4 wherein: the means for multiplying comprise analog tapped delay lines.
Claim 8
Dependent Claim
14 words
The combination according to claim 3 wherein: the means for convolving comprises charge-coupled devices.
Claim 9
Dependent Claim
15 words
The combination according to claim 7 wherein: the means for multiplying comprise charge coupled devices.
Claim 10
Dependent Claim
16 words
The combination according to claim 8 wherein: the means for multiplying comprise analog tapped delay lines.