Arithmetic circuit including electronic multiplying and dividing circuitry

Claim 2

A circuit for receiving and arithmetically combining signals representative of input factors comprising first means for providing a time base of a duration representative of a first input factor; second means comprising resistance components and capacitance components connected in circuit relation selectively representing second input factors for providing an output signal during a selected time period representative of said input factors; third means controlled by said first time base providing means for energizing said resistance and capacitance components for a duration determined by said first means; and gating means connected to said capacitance components and arranged to be activated when said capacitance components attain a predetermined energization to provide output pulses representative of the arithmetic combination of said input factors.

Claim 3

A circuit for receiving and arithmetically combining input factors comprising first means providing a time base of a duration representative of a first input factor; second means for providing output signals during a selected time period representative of second input factors, said second means comprising resistance means and capacitance means connected in series relation; means for energizing said resistance and capacitance means for a duration determined by said time base providing means; gating means connected to said capacitance means and arranged to be activated when said capacitance means charges to a predetermined level, to thereby provide output pulses representative of the arithmetic combination of said input factors, said capacitance means charging to said predetermined level of said second input factors; and counting means for counting the number of times said gating means is activated whereby the product or quotient of said input factors may be selectively obtained.

Claim 4

A circuit for receiving and arithmetically combining input factors comprising first means providing a time base of a duration representative of a first input factor; second means for providing output signals during a selected time period representative of second input factors, said second means comprising resistance means and capacitance means connected in series relation; means for energizing said resistance and capacitance means for a duration determined by said time base providing means; gating means connected to said capacitance means and arranged to be activated when said capacitance means charges to a predetermined level, to thereby provide output pulses representative of the arithmetic combination of said input factors, said capacitance means charging to said predetermined level of said second input factors; and counting means for counting the number of times said gating means is activated whereby the product or quotient of said input factors may be selectively obtained.

Claim 5

A circuit as in claim 2 wherein said gating means comprises a semiconductor device.

Claim 6

A circuit as in claim 2 wherein, a. said first and second means each comprises resistive elements connected in series with capacitance elements; and b. said gating means comprising a unijunction transistor having an emitter and two base electrodes, said emitter being connected to the junction of said resistive elements and said capacitive elements.

Claim 7

A circuit for multiplying or dividing input factors comprising, in combination, a. first and second operating circuits each including a plurality of resistive and capacitive elements selectively connected to one another; b. first and second gating means connected to said first and second circuits respectively; c. switching means energizable by signal representative of input factors for selectively connecting said resistive and capacitive elements in said circuit; d. said first gating means being actuatable when a capacitive element in said first circuit charges to a selected level to thereby discharge said capacitive element through said first gating means and provide a time base for said circuit; e. said second gating means being actuatable when a capacitive element in said second cIrcuit charges to a selected level to thereby discharge said second capacitive element through said second gating means and provides a selected number of pulses during a time selected value of time; and f. means connecting the output of said first gating means to control the operation of said second circuit and said second gating means in accordance with said time base whereby an output representative of the multiplication or division of said input factors is obtained.

Claim 8

A circuit for multiplying or dividing input factors comprising, in combination, a. first and second operating circuits each including a plurality of resistive and capacitive elements selectively connected to one another; b. first and second gating means connected to said first and second circuits respectively; c. switching means energizable by signal representative of input factors for selectively connecting said resistive and capacitive elements in said circuit; d. said first gating means being actuatable when a capacitive element in said first circuit charges to a selected level to thereby discharge said capacitive element through said first gating means and provide a time base for said circuit; e. said second gating means being actuatable when a capacitive element in said second cIrcuit charges to a selected level to thereby discharge said second capacitive element through said second gating means and provides a selected number of pulses during a time selected value of time; and f. means connecting the output of said first gating means to control the operation of said second circuit and said second gating means in accordance with said time base whereby an output representative of the multiplication or division of said input factors is obtained.

Claim 9

A circuit as in claim 5 further including, a. energizing means for developing pulses of square waveform configuration; and b. means energizeable by said first gating means to terminate said square waveform pulses.