Hybrid multiplier

Claim 2

Circuit apparatus for multiplying first and second quantities, said apparatus comprising: first signal generator means having first multistage shift register means for storing digital information corresponding to said first quantity and first digital-to-analogue converter means having first binary conditioning input means coupled to said first register means, said first converter means further having a first analogue input and a first analogue output; second signal generator means for providing an analogue signal corresponding to said second quantity; a reference signal generator for providing an analogue reference signal having a predetermined reference level; first comparator means having a first pair of inputs and an output, one of the inputs of said first pair being coupled to said reference signal generator, said first converter means having said first analogue input coupled to said output of said first comparator means and said first analogue output coupled to the input of said first comparator means to provide a feedback path for said first comparator means; second comparator means having a second pair of inputs and an output, one of the inputs of said second pair being responsive to the analogue signal of said second generator means; third signal generator means comprising: second digital-to-analogue converter means having second binary conditioning input means, a second analogue input coupled to the output of said first comparator means, and a second analogue output coupled to the other input of said second pair of said second comparator means; digital conditioning meAns having output means for conditioning said second binary conditioning input means, said digital conditioning means having an input coupled to the output of said second comparator means; and second multistage shift register means for storing the information of said digital conditioning means therein, said second register means having an input means coupled to the output means of said digital conditioning means; and control means for providing a first control signal for shifting the digital information in said first register means in the upward direction to place the most significant bit of the lastmentioned digital information in the highest order stage of said first register means whenever the last-mentioned digital information stored therein does not have a binary 1 bit in said highest order stage, and said control means providing a second control signal for shifting the information in said second register means in the downward direction in a number of shifts equal to the number of shifts required to shift the digital information in said first register means by said first control signal.

Claim 3

Circuit apparatus according to claim 1 wherein said second signal generator means further comprises: third digital-to-analogue converter means having third binary conditioning input means, a third analogue input coupled to the reference signal generator, and a third analogue output for providing the analogue signal of said second signal generator means thereat; and third multistage shift register means for storing digital information corresponding to said second quantity, said third binary conditioning input means being coupled to said third register means; said control means further providing a third control signal for shifting the digital information in said third register means in the upward direction to place the most significant bit of the last-mentioned digital information in the highest order stage of said third register means whenever the last-mentioned digital information stored therein does not have a binary one bit in said last-mentioned highest order stage, said second control signal further shifting the information in said second register means in the downward direction a number of shifts equal to the number of shifts required to shift the digital information in said third register means by said third control signal.

Claim 4

Circuit apparatus according to claim 2 wherein said second signal generator means further comprises means for converting a pulse width analogue signal corresponding to said second quantity to digital information for storing in said third register means.

Claim 5

Circuit apparatus for multiplying first and second quantities, said apparatus comprising: a first signal generator having a first buffer register for storing digital information corresponding to said first quantity, a first multistage shift register coupled to said first buffer register, and first digital-to-analogue converter having first binary conditioning input means coupled to said first shift register, said first converter having a first analogue input and a first analogue output; a second signal generator for providing an analogue signal corresponding to said second quantity; a reference signal generator for providing an analogue reference signal having a predetermined reference level; a first comparator having a first pair of first and second inputs and an output, said first input of said first pair being coupled to said reference signal generator, said first converter having said first analogue input coupled to the output of said first comparator and said first analogue output coupled to the second input of said first pair to provide a feedback path for said first comparator; a second comparator having a second pair of first and second inputs and an output, said first input of said second pair being responsive to the analogue signal of said second generator; a third signal generator comprising: a second digital-to-analogue having secOnd binary conditioning input means, a second analogue input coupled to the output of said first comparator and a second analogue output coupled to the second input of said second pair; a digital counter having output means for conditioning said second binary conditioning input means, said digital counter having an input coupled to the output of said second comparator; and a second multistage shift register for storing the information of said digital counter therein, said second shift register having an input means coupled to the output means of said digital counter; and control means for providing a first transfer signal for transferring the information in said first buffer register to said first shift register, a first control signal for shifting the digital information in said first shift register in the upward direction to place the most significant bit of the last-mentioned digital information in the highest order stage of said first register whenever the last-mentioned digital information stored therein does not have a binary one bit in said highest order stage, a second transfer signal for transferring the digital information in said digital counter into said second shift register, and a second control signal for shifting the information in said second shift register in a downward direction a number of shifts equal to the number of shifts required to shift the digital information in said first shift register by said first control signal.

Claim 6

Circuit apparatus for multiplying first and second quantities, said apparatus comprising: a first signal generator having a first buffer register for storing digital information corresponding to said first quantity, a first multistage shift register coupled to said first buffer register, and first digital-to-analogue converter having first binary conditioning input means coupled to said first shift register, said first converter having a first analogue input and a first analogue output; a second signal generator for providing an analogue signal corresponding to said second quantity; a reference signal generator for providing an analogue reference signal having a predetermined reference level; a first comparator having a first pair of first and second inputs and an output, said first input of said first pair being coupled to said reference signal generator, said first converter having said first analogue input coupled to the output of said first comparator and said first analogue output coupled to the second input of said first pair to provide a feedback path for said first comparator; a second comparator having a second pair of first and second inputs and an output, said first input of said second pair being responsive to the analogue signal of said second generator; a third signal generator comprising: a second digital-to-analogue having secOnd binary conditioning input means, a second analogue input coupled to the output of said first comparator and a second analogue output coupled to the second input of said second pair; a digital counter having output means for conditioning said second binary conditioning input means, said digital counter having an input coupled to the output of said second comparator; and a second multistage shift register for storing the information of said digital counter therein, said second shift register having an input means coupled to the output means of said digital counter; and control means for providing a first transfer signal for transferring the information in said first buffer register to said first shift register, a first control signal for shifting the digital information in said first shift register in the upward direction to place the most significant bit of the last-mentioned digital information in the highest order stage of said first register whenever the last-mentioned digital information stored therein does not have a binary one bit in said highest order stage, a second transfer signal for transferring the digital information in said digital counter into said second shift register, and a second control signal for shifting the information in said second shift register in a downward direction a number of shifts equal to the number of shifts required to shift the digital information in said first shift register by said first control signal.

Claim 7

Circuit apparatus according to claim 4 wherein said second signal generator further comprises: a third digital-to-analogue converter having third binary conditioning input means, a third analogue input coupled to the reference signal generator, and a third analogue output for providing the analogue signal of said second signal generator thereat; a third multistage shift register for storing digital information corresponding to said second quantity, said third binary conditioning input means being coupled to said third shift register; and said control means further providing a third control signal for shifting the digital information in said third shift register in the upward direction to place the most significant bit of the last-mentioned digital information in the highest order stage of said third shift register whenever the last-mentioned digital information stored therein does not have a binary one bit in said last-mentioned highest order stage, said second control signal further shifting the information in said second register in the downward direction a number of shifts equal to the number of shifts required to shift the digital information in said third register by said third control signal.

Claim 8

Circuit apparatus according to claim 5 wherein said second signal generator further comprises input digital storage means for storing digital information corresponding to said second quantity therein, said control means providing a third transfer signal for transferring the digital information in said digital storage means to said third shift register.

Claim 9

Circuit apparatus according to claim 6 wherein said input digital storage means comprises a second buffer register.

Claim 10

Circuit apparatus according to claim 6 wherein said second signal generator further comprises converter means for converting a pulse width analogue signal corresponding to said second quantity to digital information for storage in said input digital storage means.

Claim 11

Circuit apparatus according to claim 8 wherein said input digital storage means comprises a digital counter.

Claim 12

Circuit apparatus according to claim 7 wherein said second signal generator further comprises converter means for converting predetermined pulse width analogue signals corresponding to said second quantity to digital information and a digital counter for storing said last-mentioned digital information therein, and first selective switching means for selectively coupling and second buffer register and said digital counter to said third shift regIster.

Claim 13

Circuit apparatus according to claim 10 wherein said second generator further comprises an analogue signal source having an output for providing an analogue signal corresponding to said second quantity, and second selective switching means for selectively coupling said third analogue output of said third converter and said output of said analogue signal source to the first input of said second pair of inputs of said second comparator.