Dynamic digital calculating apparatus for analog functions

Claim 2

Digital calculating apparatus, comprising in combination: a. multiple-stage, pulse-responsive counter means; b. means for producing output signal representations of the numerical content of said counter; c. a pulse train source; d. means coupled to said source for feeding said train of pulses into said counter means for counting the number of said pulses; e. multiple-stage register means including an input for inserting a numerical quantity and means for at least temporarily holding said numerical quantity; f. means for producing output signal representations of the numerical content of said register; g. logic means combining the output signal representations of said counter means with those of said register means for producing signal representations of the results of said logical combinations; h. gating means; i. means coupled to the input of said counter means for feeding said train of input pulses into said gating means; and j. means for coupling the signal representations from said logic means to said gating means for selectively gating said train of pulses through said gating means in accordance with the logically combined contents of said counter and said register.

Claim 3

The invention as described in claim 1 wherein said register means comprises a second pulse-responsive, counter means and further including means for feeding a train of pulses into said second counter means.

Claim 4

The invention as described in claim 2 wherein said second counter means is characterized by being able to selectively count up or down.

Claim 5

The invention as in claim 3 further including: means for sensing the polarity of the input pulses; circuit means responsive to said sensing means for making all input pulses the same polarity; and means coupled to said sensing means for recording signal indications of the polarity of the first counter input pulses.

Claim 6

The invention as in claim 4 further including: means coupled to said second counter means for sensing a change in sign of the quantity contained in said second counter means; means responsive to said change-in-sign sensing means for recording signal indications of said change in sign; and means responsive in part to said latter means for directing the input pulses to said second counter means to count up or down.

Claim 7

The invention as set forth in claim 5 further including: another digital calculating apparatus containing a multiple-stage pulse-responsive counter means having means for producing output signal representations of the numerical content of said counter, a pulse train source, means coupled to said source for feeding said train of pulses into said counter means for counting the number of said pulses, a second pulse-responsive counter means characterized by being able to selectively count up or down, means for feeding a train of pulses into said second counter means, means for producing output signal representations of the numerical content of said second counter means, logic means combining the output signal representations of said fist counter means with those of said second counter means for producing signal representations of the results of said logical combinations, gating means, means coupled to the input of said first counter means for feeding said train of input pulses into said gating means, means for coupling the signal representations from said logic means to said gating means for selectively gating said train of pulses through said gating means in accordance with the logically combined contents of said first and second counter means, means for sensing the polarity of the input pulses to said first and second counter means, circuit means responsive to said sensing means for making the input pulses to said first and seCond counter means all of the same polarity, means coupled to said sensing means for recording signal indications of the sensed polarity of the input pulses to said first counter means; and means for feeding the output from the gating means of one of said digital calculating apparatus to the input of a counter means in the other of said digital calculating apparatus whereby the output of said one digital calculating apparatus constitutes a pulse train source for the other of said digital calculating apparatus.

Claim 8

The invention as described in claim 4 wherein said circuit means for making all input pulses the same polarity comprises: a pair of parallel circuit paths connected in common to a single input line; a separate output line for each of said parallel paths; and means responsive to the input pulse on said input line for energizing only one of said circuit paths to produce a pulse on its output line when the input pulse is positive and for energizing only the other circuit path to produce a pulse on its output line when the input pulse is negative.

Claim 9

The invention as described in claim 5 further including: circuit means operatively responsive to said polarity recording means and said change-in-sign recording means coupled to the output of said gating means for selectively controlling the polarity of the respective output pulses.

Claim 10

The invention as in claim 5 wherein said change-in-sign sensing means comprises means coupled to each stage of the second counter for producing a signal indication when the content of said second counter reaches zero.

Claim 11

A computing device using digital techniques for normally analog functions, comprising in combination: a. register means containing quantized signal representations of analog data; b. means for combining the signal representations in said register means with fixed frequency clock pulses for producing said quantized analog data in pulse train form; c. pulse-responsive counter means for summing input pulses; d. means for feeding said analog data in pulse train form from said combining means to the input of said counter means for continually summing said pulses; and e. means for producing signal output representations of the content of said counter means to provide a signal indication of the integration of the analog data.

Claim 12

A computing device using digital techniques for normally analog functions, comprising in combination: a. register means containing quantized signal representations of analog data; b. means for combining the signal representations in said register means with fixed frequency clock pulses for producing said quantized analog data in pulse train form; c. pulse-responsive counter means for summing input pulses; d. means for feeding said analog data in pulse train form from said combining means to the input of said counter means for continually summing said pulses; and e. means for producing signal output representations of the content of said counter means to provide a signal indication of the integration of the analog data.

Claim 13

The invention as set forth in claim 10 wherein said register means is a pulse-responsive counter means and further including means for continually feeding quantized data into said register means.

Claim 14

A computing device using digital techniques for normally analog functions, comprising in combination: a. multiple-stage, pulse-responsive, digital counter means; b. means for producing output signal representations of the numerical content of said counter means; c. a pulse train source; d. means for feeding the pulses from said source into said counter means for continually counting up the number of pulses; e. multiple-stage register means including an input for inserting numerical quantities and means for at least temporarily holding the inserted numerical quantities; f. means for producing output signal representations of the content of said register; g. signal responsive logic means for combining the output signal representations of said counter means with those of said register means in a predetermined logical fashion and for producing signal representations of the results of said logical combinations; h. logical gating means; i. means for feeding the pulses from said pulse train source to an input of said gating means; and j. means for coupling the signal representation from said first-mentioned logic means to another input of said gating means for selectively passing a train of pulses through said gating means for producing a pulse train which is a function of the content of said register means.

Claim 15

A computing device using digital techniques for normally analog functions, comprising in combination: a. multiple-stage, pulse-responsive, digital counter means; b. means for producing output signal representations of the numerical content of said counter means; c. a pulse train source; d. means for feeding the pulses from said source into said counter means for continually counting up the number of pulses; e. multiple-stage register means including an input for inserting numerical quantities and means for at least temporarily holding the inserted numerical quantities; f. means for producing output signal representations of the content of said register; g. signal responsive logic means for combining the output signal representations of said counter means with those of said register means in a predetermined logical fashion and for producing signal representations of the results of said logical combinations; h. logical gating means; i. means for feeding the pulses from said pulse train source to an input of said gating means; and j. means for coupling the signal representation from said first-mentioned logic means to another input of said gating means for selectively passing a train of pulses through said gating means for producing a pulse train which is a function of the content of said register means.

Claim 16

The invention as set forth in claim 12 wherein the first-mentioned logic means is arranged to produce siGnal outputs to said gating means for passing through pulses which are distributed in a substantially uniform manner along the pulse train.