Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer

Claim 1

A method of manufacturing a device in a wafer with a semiconductor body of a first conductivity type, characterized by: A. forming on a surface of the semiconductor body a layer of silicon dioxide doped with a second conductivity type dopant, B. removing that portion of the doped silicon dioxide covering the interconnect work site area of the wafer. C. forming a masking layer of an oxidation impervious medium over the wafer, D. removing the oxidation impervious masking layer from the field areas of the wafer, E. removing the doped silicon dioxide layer from field areas of the wafer so that multilayers of doped silicon dioxide and oxidation impervious medium overlay the source/drain areas and first level conductor areas of the wafer and a single layer of the oxidation impervious medium overlays the interconnect work site area of the wafer, F. forming a layer of gate oxide over the gate area of the wafer, G. forming a layer of conductive material over the entire surface of the wafer. H. forming a layer of an oxidation impervious masking medium over the entire surface of the wafer, I. removing the conductive material formed in Step G and the oxidation impervious masking medium in Step H from all areas of the wafer except the gate area of the wafer, J. exposing the wafer to an elevated temperature so as to drive the dopant in the doped silicon dioxide layer formed in Step A into the underlying semiconductor body thus forming doped source/drain diffusions and doped first level conductor diffusions, K. removing the masking medium formed in Step C from the interconnect work site area, L. doping the interconnect work site area with a second conductivity type dopant, M. forming a conductor over the entire surface of the wafer, and P1 N. removing the conductor formed in Step M from all undesired portions of the wafer surface to form a desired pattern of electrical interconnections.

Claim 2

A method of manufacturing a device in a wafer with a semiconductor body of a first conductivity type, characterized by: A. forming on a surface of the semiconductor body a layer of silicon dioxide doped with a second conductivity type dopant, B. removing that portion of the doped silicon dioxide covering the interconnect work site area of the wafer. C. forming a masking layer of an oxidation impervious medium over the wafer, D. removing the oxidation impervious masking layer from the field areas of the wafer, E. removing the doped silicon dioxide layer from field areas of the wafer so that multilayers of doped silicon dioxide and oxidation impervious medium overlay the source/drain areas and first level conductor areas of the wafer and a single layer of the oxidation impervious medium overlays the interconnect work site area of the wafer, F. forming a layer of gate oxide over the gate area of the wafer, G. forming a layer of conductive material over the entire surface of the wafer. H. forming a layer of an oxidation impervious masking medium over the entire surface of the wafer, I. removing the conductive material formed in Step G and the oxidation impervious masking medium in Step H from all areas of the wafer except the gate area of the wafer, J. exposing the wafer to an elevated temperature so as to drive the dopant in the doped silicon dioxide layer formed in Step A into the underlying semiconductor body thus forming doped source/drain diffusions and doped first level conductor diffusions, K. removing the masking medium formed in Step C from the interconnect work site area, L. doping the interconnect work site area with a second conductivity type dopant, M. forming a conductor over the entire surface of the wafer, and P1 N. removing the conductor formed in Step M from all undesired portions of the wafer surface to form a desired pattern of electrical interconnections.