Emitter coupled logic programmable logic arrays

Claim 1

A programmable logic array in a monolithic integrated circuit, said array comprising: an OR gate array including a plurality of OR gates, each of said OR gates comprising a number of transistors, each having a base which is an input to said OR gate, a collector coupled directly to a first reference potential, and an emitter, the transistor emitters in each OR gate being selectively coupled to an output thereof, so as to program said programmable logic array, and to a current source, the transistors in said OR gate array being fabricated with one collector region, a plurality of base regions disposed in said collector region such that each base region is common to every OR gate, and a plurality of emitter regions disposed in each of said base regions such that each base region includes one emitter region per OR gate; a plurality of AND gates, each of said AND gates comprising a number of transistors, each having an emitter which is coupled to one of said OR gate outputs, a base for coupling to a second reference potential, and a collector, the transistor collectors in each AND gate being coupled together to form the output of said AND gate; a first plurality of input terminals coupled to a first group of inputs of said OR gates; a second plurality of control terminals coupled to a second group of inputs of said OR gates; and a third plurality of output terminals coupled to the outputs of said AND gates.