US3784976A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic array error detection system
Assignee: International Business Machines Corp
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Filing: 1972-04-10
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Granted: 1974-01-08
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Expires: 1992-04-10
Abstract
Abstract An error detection system of n inputs is adaptable for fabrication in large scale integrated circuit form. An integrated circuit logic array provides a parity check in response to digital signals received via X and Y decoders. Reduction in the number of array cells and the X and Y driving decoder circuits is obtained by interconnecting even parity subgroups and odd parity subgroups of lines from the X and Y decoders to provide even master parity lines and odd master parity lines. A logic array having less than 2n operative cells compares the signals on the master lines and generates an error parity signal. The improvement described herein specifically separates the decoder driver circuits into independent subgroups, each having their own array comparators for handling a large number of inputs.
Inventors
- 👤 I Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 19:38
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G11; G11C; G11C17/00; G11C17/08; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/085
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
237 words
An error detection array system adaptable for implementation in monolithic form comprising: a. a plurality of m separate X and Y decoders, where m is > OR = 3, b. the X and Y decoders being responsive to a digital word having n bits of data, the n bits of data being separated into m groups, c. each of the plurality of X and Y decoders having input terminal means and a plurality of even and odd output terminal means, d. each of the X and Y decoders being independently responsive to a different one of the m groups of data to generate even parity signals and odd parity signals on their respective plurality of output terminal means, e. a logic matrix array having an ultimate parity output terminal means, the logic matrix comprising m number of subgroup matrices, each of said subgroups being connected to at least one of said even and odd output terminal means from said X decoders and also to at least one of said even and odd output terminals from said Y decoders, each of said subgroup matrices being also connected to said ultimate parity output terminal, and f. the logic matrix array being responsive to the even and odd parity signals for generating a parity output signal on said ultimate parity output terminal representative of either an even parity n bit digital word or an odd parity n bit digital word.
Claim 2
Dependent Claim
237 words
An error detection array system adaptable for implementation in monolithic form comprising: a. a plurality of m separate X and Y decoders, where m is > OR = 3, b. the X and Y decoders being responsive to a digital word having n bits of data, the n bits of data being separated into m groups, c. each of the plurality of X and Y decoders having input terminal means and a plurality of even and odd output terminal means, d. each of the X and Y decoders being independently responsive to a different one of the m groups of data to generate even parity signals and odd parity signals on their respective plurality of output terminal means, e. a logic matrix array having an ultimate parity output terminal means, the logic matrix comprising m number of subgroup matrices, each of said subgroups being connected to at least one of said even and odd output terminal means from said X decoders and also to at least one of said even and odd output terminals from said Y decoders, each of said subgroup matrices being also connected to said ultimate parity output terminal, and f. the logic matrix array being responsive to the even and odd parity signals for generating a parity output signal on said ultimate parity output terminal representative of either an even parity n bit digital word or an odd parity n bit digital word.
Claim 3
Dependent Claim
78 words
An error detection array system adaptable for implementation in monolithic form as in claim 1 wherein: a. each of the separate X and Y decoders comprises a plurality of decoder logic circuits, and b. the total number of X and Y decoder logic circuits for n even bits of data is less than 2(n/2 1), and the total number of X and Y decoder logic circuits for n odd bits of data is less than 3 (2n/2 1/2).
Claim 4
Dependent Claim
28 words
An error detection array system adaptable for implementation in monolithic form as in claim 2 wherein: a. each of the m subgroups comprises less than 2n/2 functional cells.
Claim 5
Dependent Claim
55 words
An error detection array system adaptable for implementation in monolithic form as in claim 3 wherein: a. each of the m plurality of X and Y decoders include a first means for interconnecting a plurality of the even output terminals together and a second means for interconnecting a plurality of the odd output terminals together.
Claim 6
Dependent Claim
28 words
An error detection array system adaptable for implementation in monolithic form as in claim 4 wherein: a. each of the first and second means comprises a wired-OR interconnection.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-07 | 1977-07-09 | 1978-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-07 | 1981-07-09 | 1982-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-07 | 1985-07-09 | 1986-01-08 | $7700.00 | Window Closed / Lapsed |