Non-saturating emitter-coupled multi-level rtl-circuit logic circuit

Claim 1

THE COMBINATION COMPRISING: A FIRST EMITTER FOLLOWER LOGIC GATE INCLUDING A PLURALITY OF TRANSISTORS HAVING THEIR EMITTER-COLLECTOR NECTED IN PARALLEL; A SECOND EMITTER FOLLOWER LOGIC GATE INCLUDING A PLURALITY OF TRANSISTORS HAVING THEIR EMITTER-COLLECTOR PATHS CONNECTED IN PARALLEL; MEANS COUPLING THE OUTPUT OF THE FIRST LOGIC GATE TO THE INPUT OF ONE OF THE TRANSISTORS OF THE SECOND LOGIC GATE; SEPARATE MEANS FOR APPLYING INPUT SIGNALS TO THE INPUTS OF THE OTHER TRANSISTORS IN THE SECOND LOGIC GATE; AN EMITTER COUPLED CURRENT STEERING LOGIC GATE INCLUDING AT LEAST FIRST AND SECOND TRANSISTORS HAVING THEIR EMITTERS CONNECTED TOGETHER; A RESISTOR CONNECTED IN THE COMMON EMITTER CIRCUIT OF SAID FIRST AND SECOND TRANSISTORS; MEANS FOR APPLYING A FIXED POTENTIAL AT THE BASE OF THE FIRST TRANSISTOR IN THE CURRENT STEERING LOGIC GATE; MEANS CONNECTING THE BASE OF THE SECOND TRANSISTOR TO THE OUTPUT OF THE SECOND LOGIC GATE; AND OUTPUT MEANS CONNECTED AT THE COLLECTOR OF ONE OF THE FIRST AND SECOND TRANSISTORS.