Patent US4307308A successfully refreshed from Google Patents.
US4307308A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital signal conversion circuit
Assignee: Verizon Laboratories Inc
•
Filing: 1979-11-19
•
Granted: 1981-12-22
•
Expires: 1999-11-19
Abstract
Abstract Circuit for converting input signals at TTL voltage levels to output signals at voltage levels for use with MOS logic circuits. The circuit employs an arrangement of NMOS FET's. Six FET's are arranged in pairs to form three inverters. Another FET is connected in series between the input terminal and different portions of the first and second of the three inverters. The output of the second inverter is fed back to the gate electrode of one of the FET's of the first inverter and to the gate electrode of the series connected FET. The output of the second inverter is also applied to the third inverter. The excursion between voltage levels representing logic 1 and logic 0 at the output of the third inverter is greater than the excursion between voltage levels representing logic 1 and logic 0 at the input to the circuit.
Inventors
- 👤 Jun-ichi Sano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
288 words
A digital signal conversion circuit comprising an input terminal for receiving input signals having a first voltage condition or a second voltage condition; a first field effect transistor connected in series between the input terminal and a first connection point; a second field effect transistor connected between the first connection point and a point of reference potential; a third field effect transistor connected between a source of operating potential and the first connection point; a fourth field effect transistor connected between a second connection point and the point of reference potential; and a fifth field effect transistor connected between the source of operating potential and the second connection point; the first connection point being connected to the gate of the fourth field effect transistor; the second connection point being connected to the gate of the first field effect transistor and to the gate of the second field effect transistor; said first field effect transistor being operable in response to a first voltage condition at the input terminal to produce a voltage at the first connection point biasing the fourth field effect transistor to a high impedance condition thereby producing a third voltage condition at the second connection point; said first field effect transistor being operable in response to a second voltage condition at the input terminal to produce a voltage at the first connection point biasing the fourth field effect transistor to a low impedance condition thereby producing a fourth voltage condition at the second connection point; and said first and second field effect transistors being biased to conduction in response to said third voltage condition at the second connection point and being biased to nonconduction in response to said fourth voltage condition at the second connection point.
Claim 2
Dependent Claim
288 words
A digital signal conversion circuit comprising an input terminal for receiving input signals having a first voltage condition or a second voltage condition; a first field effect transistor connected in series between the input terminal and a first connection point; a second field effect transistor connected between the first connection point and a point of reference potential; a third field effect transistor connected between a source of operating potential and the first connection point; a fourth field effect transistor connected between a second connection point and the point of reference potential; and a fifth field effect transistor connected between the source of operating potential and the second connection point; the first connection point being connected to the gate of the fourth field effect transistor; the second connection point being connected to the gate of the first field effect transistor and to the gate of the second field effect transistor; said first field effect transistor being operable in response to a first voltage condition at the input terminal to produce a voltage at the first connection point biasing the fourth field effect transistor to a high impedance condition thereby producing a third voltage condition at the second connection point; said first field effect transistor being operable in response to a second voltage condition at the input terminal to produce a voltage at the first connection point biasing the fourth field effect transistor to a low impedance condition thereby producing a fourth voltage condition at the second connection point; and said first and second field effect transistors being biased to conduction in response to said third voltage condition at the second connection point and being biased to nonconduction in response to said fourth voltage condition at the second connection point.
Claim 3
Dependent Claim
21 words
A digital signal conversion circuit in accordance with claim 1 wherein said first field effect transistor is of the depletion type.
Claim 4
Dependent Claim
23 words
A digital signal conversion circuit in accordance with claim 2 wherein said second and fourth field effect transistors are of the enhancement type.
Claim 5
Dependent Claim
78 words
A digital signal conversion circuit in accordance with claim 1 including inverting means having an input connection connected to said second connection point and having an output connection, said inverting means being operable to produce a fifth voltage condition at the output connection when a third voltage condition is present at the second connection point and to produce a sixth voltage condition at the output connection when a fourth voltage condition is present at the second connection point.
Claim 6
Dependent Claim
128 words
A digital signal conversion circuit in accordance with claim 4 wherein said inverting means includes a sixth field effect transistor connected between the output connection and the point of reference potential and having its gate connected to the second connection point; and a seventh field effect transistor connected between the source of operating potential and the output connection; said sixth field effect transistor being biased to a low impedance condition in response to the presence of said third voltage condition at the second connection point thereby producing the fifth voltage condition at the output connection and being biased to a high impedance condition in response to the presence of said fourth voltage condition at the second connection point thereby producing the sixth voltage condition at the output connection.
Claim 7
Dependent Claim
35 words
A digital signal conversion circuit in accordance with claim 5 wherein said first field effect transistor is of the depletion type; and said second, fourth, and sixth field effect transistors are of the enhancement type.
Claim 8
Dependent Claim
195 words
A digital signal conversion circuit in accordance with claim 4 wherein said first field effect transistor is operable in response to a voltage level at the input terminal less than a first predetermined voltage to produce a voltage at the first connection point biasing the fourth field effect transistor to a high impedance condition, and is operable in response to a voltage level at the input terminal greater than a second predetermined voltage to produce a voltage at the first connection point biasing the fourth field effect transistor to a low impedance condition; and said inverting means is operable to produce an output voltage at one predetermined voltage level at its output connection when a third voltage condition is present at the second connection point and to produce an output voltage at another predetermined voltage level at its output connection when a fourth voltage condition is present at the second connection point; the voltage excursion between said one predetermined voltage level and said other predetermined voltage level at the output connection of the inverting means being greater than the voltage excursion between said first predetermined voltage and said second predetermined voltage at the input terminal.
Claim 9
Dependent Claim
209 words
A digital signal conversion circuit comprising an input terminal for receiving input signals having a first voltage condition or a second voltage condition; a first field effect transistor of the depletion type connected in series between the input terminal and a first connection point; a second field effect transistor of the enhancement type connected between the first connection point and a point of reference potential; a third field effect transistor of the depletion type connected between a source of operating potential and the first connection point; a fourth field effect transistor of the enhancement type connected between a second connection point and the point of reference potential; a fifth field effect transistor of the depletion type connected between the source of operating potential and the second connection point; the gates of the third and fourth field effect transistors being connected to the first connection point; the gates of the first, second, and fifth field effect transistors being connected to the second connection point. whereby when a first voltage condition is present at the input terminal a third voltage condition is produced at the second connection point and when a second voltage condition is present at the input terminal a fourth voltage condition is produced at the second connection point.
Claim 10
Dependent Claim
209 words
A digital signal conversion circuit comprising an input terminal for receiving input signals having a first voltage condition or a second voltage condition; a first field effect transistor of the depletion type connected in series between the input terminal and a first connection point; a second field effect transistor of the enhancement type connected between the first connection point and a point of reference potential; a third field effect transistor of the depletion type connected between a source of operating potential and the first connection point; a fourth field effect transistor of the enhancement type connected between a second connection point and the point of reference potential; a fifth field effect transistor of the depletion type connected between the source of operating potential and the second connection point; the gates of the third and fourth field effect transistors being connected to the first connection point; the gates of the first, second, and fifth field effect transistors being connected to the second connection point. whereby when a first voltage condition is present at the input terminal a third voltage condition is produced at the second connection point and when a second voltage condition is present at the input terminal a fourth voltage condition is produced at the second connection point.
Claim 11
Dependent Claim
78 words
A digital signal conversion circuit in accordance with claim 8 including inverting means having an input connection connected to said second connection point and having an output connection, said inverting means being operable to produce a fifth voltage condition at the output connection when a third voltage condition is present at the second connection point and to produce a sixth voltage condition at the output connection when a fourth voltage condition is present at the second connection point.
Claim 12
Dependent Claim
149 words
A digital signal conversion circuit in accordance with claim 9 wherein said inverting means includes a sixth field effect transistor of the enhancement type connected between the output connection and the point of reference potential and having its gate connected to the second connection point; a seventh field effect transistor of the depletion type connected between the source of operating potential and the output connection and having its gate connected to the output connection; said sixth field effect transistor being biased to a low impedance condition in response to the presence of said third voltage condition at the second connection point thereby producing the fifth voltage condition at the output connection; and said sixth field effect transistor being biased to a high impedance condition in response to the presence of said fourth voltage condition at the second connection point thereby producing the sixth voltage condition at the output connection.
Claim 13
Dependent Claim
158 words
A digital signal conversion circuit in accordance with claim 10 wherein said first field effect transistor is operable in response to a voltage level at the input terminal less than a first predetermined voltage to produce a voltage at the first connection point biasing the fourth field effect transistor to a high impedance condition, and is operable in response to a voltage level at the input terminal greater than a second predetermined voltage to produce a voltage at the first connection point biasing the fourth field effect transistor to a low impedance condition; and said inverting means produces a voltage level at its output connection close to the voltage of the point of reference potential when the sixth field effect transistor is in a low impedance condition and produces a voltage level at its output connection close to the voltage of the source of operating potential when the sixth field effect transistor is in a high impedance condition.
Claim 14
Dependent Claim
22 words
A digital signal conversion circuit in accordance with claim 11 wherein said field effect transistors are N channel metal-oxide-silicon field effect transistors.
Claim 15
Dependent Claim
25 words
A digital signal conversion circuit in accordance with claim 12 wherein the input terminal is connected to a transistor-transistor-logic circuit which produces the input signals.
References Cited (Backward Citations)
US3612908A
Cited
US4035662A
Cited
US3916430A
Cited
US4000411A
Cited
US4039860A
Cited
US4074148A
Cited
US4096402A
Cited
US4032795A
Cited
US4023050A
Cited
US4181865A
Cited
US4128775A
Cited
US4110633A
Cited
US4264829A
Cited
US4256974A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-21 | 1985-06-22 | 1985-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-21 | 1989-06-22 | 1989-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-21 | 1993-06-22 | 1993-12-22 | $7700.00 | Window Closed / Lapsed |