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US4287435A Expired / Lapsed US ⏱️ 0.0 years remaining

Complementary transistor inverting emitter follower circuit

Assignee: International Business Machines Corp
•
Filing: 1979-10-05
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Granted: 1981-09-01
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Expires: 1999-10-05
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Abstract

Abstract A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the V be necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other. In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal. In a logic circuit species of the invention, the emitter of one of the second pair of transistors is connected to the base of the other of the second pair of transistors. NOR logic is performed by connecting additional transistors in parallel with said one of the second pair of transistors, the bases of the additional transistors receiving respective logic input signals. The output from the driver circuit as well as from the logic circuit is derived from the commonly connected emitters of the first pair of transistors. The first pair of transistors conduct only during the transitions of the input signals.

Inventors

  • 👤 Joseph R. Cavaliere
  • 👤 Robert A. Henle
  • 👤 Richard R. Konian
  • 👤 James L. Walsh

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 19:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K5/00; H03K5/01; H03K5/02

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 127 words
A complementary transistor, inverting emitter follower circuit comprising: a series-connected first pair of bipolar complementary transistors, the emitter electrodes of said first pair of transistors being connected together and to an output terminal, a second pair of complementary bipolar transistors, the collector electrodes of said second pair of transistors being directly connected to respective bases of said first pair of transistors of similar kind, one of the remaining electrodes of said second pair of transistors being connected together, at least one base of said second pair of transistors being connected to an input terminal, and means connected to the collectors and emitters of said second pair of transistors and to the collectors of said first pair of transistors for biasing said first and second pairs of transistors.
Claim 2
Dependent Claim 127 words
A complementary transistor, inverting emitter follower circuit comprising: a series-connected first pair of bipolar complementary transistors, the emitter electrodes of said first pair of transistors being connected together and to an output terminal, a second pair of complementary bipolar transistors, the collector electrodes of said second pair of transistors being directly connected to respective bases of said first pair of transistors of similar kind, one of the remaining electrodes of said second pair of transistors being connected together, at least one base of said second pair of transistors being connected to an input terminal, and means connected to the collectors and emitters of said second pair of transistors and to the collectors of said first pair of transistors for biasing said first and second pairs of transistors.
Claim 3
Dependent Claim 16 words
The circuit defined in claim 1 wherein said output terminal is connected to a capacitive load.
Claim 4
Dependent Claim 19 words
The circuit defined in claim 2 wherein the bases of said second pair of transistors are directly connected together.
Claim 5
Dependent Claim 27 words
The circuit defined in claim 2 wherein the emitter of one and the base of the other of said second pair of transistors are directly connected together.
Claim 6
Dependent Claim 30 words
The circuit defined in claim 4 wherein said means for biasing said transistors includes means for separately biasing the emitter of the PNP transistor of said second pair of transistors.
Claim 7
Dependent Claim 42 words
The circuit defined in claim 4 and further including additional transistors connected in parallel with the NPN transistor of said second pair of transistors, separate logic input signals being applied to the bases of said additional transistors and of said NPN transistor.

References Cited (Backward Citations)

US3433978A Cited
US3458719A Cited
US3509363A Cited
US3614467A Cited
US3798471A Cited
US3854057A Cited
US4053792A Cited
US3987310A Cited
US4006365A Cited
US4045689A Cited
US4065678A Cited
US4064405A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-08-31 1985-03-02 1985-09-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-08-31 1989-03-02 1989-09-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-08-31 1993-03-02 1993-09-01 $7700.00 Window Closed / Lapsed

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