US4053792A
Expired / Lapsed
US
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Low power complementary field effect transistor (cfet) logic circuit
Assignee: International Business Machines Corp
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Filing: 1974-06-27
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Granted: 1977-10-11
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Expires: 1994-06-27
Abstract
Abstract Disclosed is a logic circuit implemented in complementary field effect transistor (CFET) technology for improving the transient response of CFET circuits and providing a true DOT-OR or DOT-AND logic function. The pull-up circuit includes at least one active device and is placed either in parallel with or replaces the conventional load impedance between a source of potential and the output node.
Inventors
- 👤 Anthony T. Cannistra
- 👤 Joseph A. Petrosky, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
132 words
A complementary field effect transistor logic circuit comprising: an output node; a first plurality of transistors of a first channel type connected in parallel between a first potential level and said output node, each said transistor receiving an input signal at a control electrode; a pull-up transistor of a second channel type connected between said output node and a second potential level; impedance means connected between said second potential level and a control electrode of said pull-up transistor; and a second plurality of transistors of said second channel type connected in electrical series between said first potential level and the control electrode of said pull-up transistor, each said second plurality of transistors having a control electrode receiving an input corresponding to each of the inputs received by said first plurality of transistors.
Claim 2
Dependent Claim
132 words
A complementary field effect transistor logic circuit comprising: an output node; a first plurality of transistors of a first channel type connected in parallel between a first potential level and said output node, each said transistor receiving an input signal at a control electrode; a pull-up transistor of a second channel type connected between said output node and a second potential level; impedance means connected between said second potential level and a control electrode of said pull-up transistor; and a second plurality of transistors of said second channel type connected in electrical series between said first potential level and the control electrode of said pull-up transistor, each said second plurality of transistors having a control electrode receiving an input corresponding to each of the inputs received by said first plurality of transistors.
Claim 3
Dependent Claim
184 words
A complementary field effect transistor logic circuit comprising: an output node; a first plurality of transistors of a first channel type connected in parallel between a first potential level and said output node, a control electrode of each said first plurality of transistors receiving an input signal; a pull-up transistor of a second channel type connected between said output node and said second potential level; a second plurality of field effect transistors of said second channel type connected between said first potential level and a control electrode of said pull-up transistor, each said second plurality of transistors receiving an input signal at its control electrode corresponding to an input signal received by each said plurality of transistors of said first channel type; and a third plurality of transistors of said second channel type connected between said second potential level and a current path defined by said second plurality of transistors, each said third plurality of transistors receiving at its control electrode a complemented input signal corresponding to an input signal received at the control electrode of each said first and second plurality of transistors.
Claim 4
Dependent Claim
184 words
A complementary field effect transistor logic circuit comprising: an output node; a first plurality of transistors of a first channel type connected in parallel between a first potential level and said output node, a control electrode of each said first plurality of transistors receiving an input signal; a pull-up transistor of a second channel type connected between said output node and said second potential level; a second plurality of field effect transistors of said second channel type connected between said first potential level and a control electrode of said pull-up transistor, each said second plurality of transistors receiving an input signal at its control electrode corresponding to an input signal received by each said plurality of transistors of said first channel type; and a third plurality of transistors of said second channel type connected between said second potential level and a current path defined by said second plurality of transistors, each said third plurality of transistors receiving at its control electrode a complemented input signal corresponding to an input signal received at the control electrode of each said first and second plurality of transistors.
Claim 5
Dependent Claim
45 words
A complementary field effect transistor logic circuit as in claim 2 further comprising: an inverter circuit connected between the control electrode of each said first and second plurality of field effect transistors and the control electrode of each said third plurality of field effect transistors.
Claim 6
Dependent Claim
89 words
A complementary field effect transistor logic circuit as in claim 3 in which said inverter circuit comprises: a pair of series connected field effect transistors of first and second channel type forming a series electrical path between said first and second potential levels, a common point therebetween forming an output node connected to the control electrode of each said third plurality of transistors, the gate electrodes of each said pair of transistors being connected to the control electrodes of each said first and second plurality of field effect transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-10 | 1981-04-11 | 1981-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-10 | 1985-04-11 | 1985-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-10 | 1989-04-11 | 1989-10-11 | $7700.00 | Window Closed / Lapsed |