Logically controlled inverter

Claim 2

A logically controlled inverter circuit comprising: a capacitive load; a first field effect transistor connected in series with said capacitive load; a second field effect transistor connected in parallel with said capacitive load, thereby charging and discharging said capacitive load via said first and second field effect transistor, respectively, by applying suitabLe gate potentials; a resistive means connected between said first field effect transistor and a source of potential supply; and a third field effect transistor connected in series with said capacitive load, and having a gate electrically connected to a point between said resistive means and said first field effect transistor, thereby rendering said third field effect transistor conductive and applying a defined potential to the capacitive load when said first field effect transistor is inhibited; wherein said third field effect transistor applies the potential at the gate of the first field effect transistor to the capacitive load.

Claim 3

A logically controlled inverter circuit as in claim 1, wherein for the dynamic operation of the inverter a capacitance is arranged parallel to said first field effect transistor.

Claim 4

A logically controlled inverter circuit as in claim 1 wherein said resistive means comprises a high-resistance fourth field effect transistor.

Claim 5

A logically controlled inverter circuit as in claim 3 wherein the gate and drain electrodes of said fourth field effect transistor are connected to said source of potential supply.

Claim 6

A logically controlled inverter circuit as in claim 4 comprising additional field effect transistors including at least a fifth field effect transistor arranged in parallel with said second field effect transistor, forming a NOR circuit.

Claim 7

A logically controlled inverter circuit as in claim 1 comprising at least one additional field effect transistor connected in series with said second field effect transistor and in parallel with said capacitive load, forming a NAND circuit.

Claim 8

A logically controlled inverter circuit comprising: a capacitive load; a first field effect transistor connected in series with said capacitive load; a second field effect transistor connected in parallel with said capacitive load, thereby charging and discharging said capacitive load via said first and second field effect transistor, respectively, by applying suitable gate potentials; a resistive means connected between said first field effect transistor and a source of potential supply; and a third field effect transistor connected in series with said capacitive load, and having a gate electrically connected to a point between said resistive means and said first field effect transistor, thereby rendering said third field effect transistor conductive and applying a defined potential to the capacitive load when said first field effect transistor is inhibited; wherein said resistive means comprises a high-resistance fourth field effect transistor; wherein the gate and drain electrodes of said fourth field effect transistor are connected to said source of potential supply; including additional field effect transistors including at least a fifth field effect transistor arranged in parallel with said second field effect transistor, forming a NOR circuit.

Claim 9

A logically controlled inverter circuit comprising: a capacitive load; a first field effect transistor connected in series with said capacitive load; a second field effect transistor connected in parallel with said capacitive load, thereby charging and discharging said capacitive load via said first and second field effect transistor, respectively, by applying suitable gate potentials; a resistive means connected between said first field effect transistor and a source of potential supply; and a third field effect transistor connected in series with said capacitive load, and having a gate electrically connected to a point between said resistive means and said first field effect transistor, thereby rendering said third field effect transistor conductive and applying a defined potential to the capacitive load when said first field effect transistor is inhibited; wherein said resistive means comprises a high-resistance fourth field effect transistor; wherein the gate and drain electrodes of said fourth field effect transistor are connected to said source of potential supply; including additional field effect transistors including at least a fifth field effect transistor arranged in parallel with said second field effect transistor, forming a NOR circuit.