US3582683A
Expired / Lapsed
US
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Optionally clocked transistor circuits
Assignee: Bunker Ramo Corp
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Filing: 1968-08-09
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Granted: 1971-06-01
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Expires: 1988-08-09
Abstract
Abstract Inverting switching and logic function circuits for digital equipment are provided in networks with an option for phase clocking by including first and second insulated-gate (MOS), field-effect transistors having their source connected to the functional circuit output terminal. The drain and gate of the first transistor are adapted to be connected to a clock source for clocked mode of operation and to circuit ground for nonclocked mode of operation. The gate of the first transistor is also so connected to the functional circuit as to provide circuit ground thereto permanently for a nonclocked mode of operation, and to provide clock pulses thereto for a clocked mode of operation, such that the functional circuit is biased off in reference to circuit ground potential during clock pulses to charge stray capacitance at the functional circuit output terminal, but enabled as a function of one or more input signals between clock pulses to discharge the stray capacitance. The second transistor connected to the output terminal is adapted to be biased for conduction as a load transistor when the first transistor is connected to circuit ground such that the stray capacitance is then charged through the load transistor and discharged through the circuit as a function of one or more input signals in a nonclocked mode of operation for the network.
Inventors
- 👤 George V Podraza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0944; H03K19/09441
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
73 words
The combination as defined in claim 1 wherein said first device is an insulated-gate, field-effect transistor, said first and second terminals comprise the respective source and drain thereof, and said third terminal comprises the gate thereof, and said second device is an insulated-gate, field-effect transistor, said first and second terminals of said second device comprise the respective source and drain thereof, and said third terminal of said second device comprises the gate thereof.
Claim 2
Dependent Claim
18 words
The combination as defined in claim 2 wherein said functional circuit is comprised entirely of insulated-gate, field-effect transistors.
Claim 3
Dependent Claim
47 words
The combination as defined in claim 2 wherein said functional circuit comprises at least one insulated-gate, field-effect transistor having its source connected to the gate of said first device, its drain connected to said output terminal, and its gate adapted to be connected to a signal source.
Claim 4
Dependent Claim
49 words
The combination as defined in claim 2 wherein said functional circuit comprises a plurality of insulated-gate, field-effect transistors, each having its source connected to the gate of said first device, its drain connected to said output terminal, and its gate adapted to be connected to a separate signal source.
Claim 5
Dependent Claim
94 words
The combination as defined in claim 2 wherein said functional circuit comprises: at least one insulated-gate, field-effect transistor having its source connected to the gate of said first device, its drain connected to said output terminal, and its gate adapted to be connected to a signal source; and at least one pair of field-effect transistors connected in series, the source of one connected to the gate of said first device, the drain of the other connected to said output terminal, and the gate of each adapted to be connected to a separate signal source.
Claim 6
Dependent Claim
72 words
The combination as defined in claim 2 wherein said functional circuit comprises a plurality of insulated-gate, field-effect transistors connected in series, the source of one connected to the gate of said first device, the drain of each but the last connected to the source of the next, the drain of the last connected to said output terminal, and the gate of each being adapted to be connected to a separate signal source.
Claim 7
Dependent Claim
158 words
The combination as defined in claim 2 wherein said functional circuit is a multibranch, multistage selector tree comprised entirely of insulated-gate, field-effect transistors, each stage but the first comprising a transistor in each branch, each transistor having its source connected to a node of a preceding stage and its gate being adapted to be connected to a separate control signal source, the first stage comprising a transistor in each branch having its source connected in series with an input transistor and its gate being adapted to be connected to a separate control signal source, each input transistor having its source connected to the gate of said first transistor and its gate being adapted to be connected to a separate data signal source, and the last stage having its node connected to said output terminal, whereby a data source signal is selectively transmitted in complementary form from said output terminal in response to signals from said control signal sources.
Claim 8
Dependent Claim
257 words
In an MOSFET structured functional network having at least one transistor in a functional circuit to be selectively switched on by a digital signal to provide at its drain 0 volts, and switched off by the binary complement of said digital signal to provide at its drain some predetermined minimum voltage, apparatus for optionally clocking operation of said network comprising: a first transistor having its source connected to the drain of said one transistor, its drain connected to a supply voltage substantially equal to said minimum voltage, and its gate adapted to be connected to a first source of bias voltage of the same polarity as said drain voltage and of a value equal to at least the voltage of said drain supply voltage for operation of said circuit in a nonclocked mode, and to a second source of bias voltage sufficient to cut off current through the drain of said first transistor for operation of said circuit in a clocked mode; a second transistor having its source connected to the drain of said one transistor and its drain connected to its gate; and direct current means connecting the gate of said second transistor to the source of said one transistor, the gate of said second transistor being adapted to be connected to a source of 0 volts for operation of said circuit in a nonclocked mode, and to a source of clock pulses of a polarity and amplitude for switching said second transistor into conduction at saturation for operation of said circuit in a clocked mode.
Claim 9
Dependent Claim
34 words
Apparatus as defined in claim 9 wherein said first source of bias voltage is equal to twice the value of said drain supply voltage, and said second source of bias voltage is 0 volts.
Claim 10
Dependent Claim
24 words
Apparatus as defined in claim 9 wherein said clock pulse source returns the gate of said second transistor to substantially 0 volts between pulses.
Claim 11
Dependent Claim
44 words
Apparatus as defined in claim 9 wherein said circuit comprises said one transistor having its drain connected to the sources of said first and second transistors, and said coupling means comprises a direct connection between its source and the gate of said second transistor.
Claim 12
Dependent Claim
60 words
Apparatus as defined in claim 9 wherein said circuit comprises a plurality of transistors connected in series, said one transistor being at one end of the series, and said coupling means comprises a direct connection between the source of the one of said plurality of transistors at the other end of the series and the gate of said second transistor.
Claim 13
Dependent Claim
26 words
Apparatus as defined in claim 13 including a second plurality of transistors connected in series, said second series being connected in parallel with said first series.
Claim 14
Dependent Claim
29 words
Apparatus as defined in claim 13 including a second plurality of transistors connected in series, said second series being connected in parallel with a portion of said first series.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |