US3678293A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-biasing inverter
Assignee: Arris Technology Inc
•
Filing: 1971-01-08
•
Granted: 1972-07-18
•
Expires: 1991-01-08
Abstract
Abstract A self-biasing inverter circuit comprises a load device and a semiconductor driving field effect transistor connected in series with a low-impedance device across a voltage source. The input is impressed on the gate terminal of the driving FET and the output is taken off the junction between the driving FET and the load device. A second field effect transistor having a high output impedance is connected between the source of the driving FET and the negative side of the voltage source and has its gate terminal connected to the inverter output. In this manner the source of the driving FET is biased to a negative voltage level sufficient to maintain said driving FET in the nonconductive state even for logic ''''O'''' signal more negative than threshold. In addition the bias signal is automatically diminished as a logic ''''1'''' input is impressed on the gate of the driving FET to aid in rendering the driving FET conductive.
Inventors
- 👤 Jay D Popper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384; H03K19/01; H03K19/017; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
225 words
In a self-biasing logic circuit having an input port, an output port, and a source of first and second reference voltage levels, a first semiconductor switching device having a control terminal and first and second output terminals, said output terminals of said first switching device being operatively connected between said first and second reference voltage levels, a second semiconductor switching device having a control terminal and first and second output terminals, said output terminals of said second switching device being connected between said first output terminal of said first switching device and said source of said first voltage level, said second output terminal of said first switching device being operatively connected to said control terminal of said second switching device, said control terminal of said first switching device being connected to said input port independently of said second switching device, said output port being defined at the junction of said second output terminal of said first switching device and said control terminal of said second switching device, whereby application of a signal at said input port sufficient to change the conductance of said first switching device in a given sense is effective to change the conductance of said second switching device in the opposite sense thereby to increase the driving potential across said control terminal and said first output terminal of said first switching device.
Claim 2
Dependent Claim
225 words
In a self-biasing logic circuit having an input port, an output port, and a source of first and second reference voltage levels, a first semiconductor switching device having a control terminal and first and second output terminals, said output terminals of said first switching device being operatively connected between said first and second reference voltage levels, a second semiconductor switching device having a control terminal and first and second output terminals, said output terminals of said second switching device being connected between said first output terminal of said first switching device and said source of said first voltage level, said second output terminal of said first switching device being operatively connected to said control terminal of said second switching device, said control terminal of said first switching device being connected to said input port independently of said second switching device, said output port being defined at the junction of said second output terminal of said first switching device and said control terminal of said second switching device, whereby application of a signal at said input port sufficient to change the conductance of said first switching device in a given sense is effective to change the conductance of said second switching device in the opposite sense thereby to increase the driving potential across said control terminal and said first output terminal of said first switching device.
Claim 3
Dependent Claim
28 words
The logic circuit of claim 1, wherein said first switching device has a relatively low output impedance and said second switching device has a relatively high output impedance.
Claim 4
Dependent Claim
26 words
The logic circuit of claIm 1, wherein said first semiconductor switching device is a field effect transistor, said control terminal thereof comprising the gate electrode thereof.
Claim 5
Dependent Claim
26 words
The logic circuit of claim 2, wherein said first semiconductor switching device is a field effect transistor, said control terminal thereof comprising the gate electrode thereof.
Claim 6
Dependent Claim
26 words
The logic circuit of claim 1, wherein said second semiconductor switching device is a field effect transistor, said control terminal thereof comprising the gate electrode thereof.
Claim 7
Dependent Claim
26 words
The logic circuit of claim 2, wherein said second semiconductor switching device is a field effect transistor, said control terminal thereof comprising the gate electrode thereof.
Claim 8
Dependent Claim
26 words
The logic circuit of claim 3, wherein said second semiconductor switching device is a field effect transistor, said control terminal thereof comprising the gate electrode thereof.
Claim 9
Dependent Claim
104 words
The logic circuit of claim 1, further comprising a third semiconductor device connected between said first output terminal of said first semiconductor switching device and a source of said second voltage level, whereby when said second semiconductor switching device is conductive current flows through said second and third semiconductor devices to bias said first output terminal of said first semiconductor switching device to a given voltage level between said first and second voltage levels and when said second semiconductor switching device is rendered nonconductive, the voltage level at said first output terminal of said first semiconductor switching device moves toward said second voltage level.
Claim 10
Dependent Claim
27 words
The logic circuit of claim 8, wherein said first switching device has a low output impedance and said second switching device has a relatively high output impedance.
Claim 11
Dependent Claim
26 words
The logic circuit of claim 8, wherein said first semiconductor switching device is a field effect transistor, said control terminal thereof comprising the gate electrode thereof.
Claim 12
Dependent Claim
26 words
The logic circuit of claim 8, wherein said second semiconductor switching device is a field effect transistor, said control terminal thereof comprising the gate electrode thereof.
Claim 13
Dependent Claim
31 words
The logic circuit of claim 8, wherein said third semiconductor device is a switching device, the control terminal of which is operatively connected to said source of said first voltage level.
Claim 14
Dependent Claim
64 words
The logic circuit of claim 1, wherein said input port is adapted to receive signals at first and second logic levels corresponding to said first and second voltage levels, respectively, and further comprising a semiconductor load device connected between said second output terminal of said first switching device and a source of said first voltage level, whereby said logic circuit functions as an inverter.
Claim 15
Dependent Claim
158 words
In a self-biasing logic circuit having an input port, an output port and a reference voltage source having first and second reference voltage levels, a first semiconductor switching device having a control terminal and first and second output terminals, said output terminals being operatively connected across said voltage source between said first and second reference voltage levels, impedance means connected between said first output terminal of said first semiconductor switching device and said first reference voltage level of said voltage source, the control terminal of said first semiconductor switching device being operatively connected to said input port, said second output terminal of said first semiconductor switching device being connected to said output port, and means responsive to the signal at said output port for varying the impedance of said impedance means, thereby to vary the voltage level at said first output terminal of said first semiconductor switching device in accordance with the output signal at said output port.
Claim 16
Dependent Claim
158 words
In a self-biasing logic circuit having an input port, an output port and a reference voltage source having first and second reference voltage levels, a first semiconductor switching device having a control terminal and first and second output terminals, said output terminals being operatively connected across said voltage source between said first and second reference voltage levels, impedance means connected between said first output terminal of said first semiconductor switching device and said first reference voltage level of said voltage source, the control terminal of said first semiconductor switching device being operatively connected to said input port, said second output terminal of said first semiconductor switching device being connected to said output port, and means responsive to the signal at said output port for varying the impedance of said impedance means, thereby to vary the voltage level at said first output terminal of said first semiconductor switching device in accordance with the output signal at said output port.
Claim 17
Dependent Claim
36 words
The logic circuit of claim 14, wherein said impedance device is a second semiconductor device having a relatively high output impedance, the control terminal of said second semiconductor device being operatively connEcted to said output port.
Claim 18
Dependent Claim
114 words
In a self-biasing logic circuit having an input port, an output port and a source of first and second reference voltage levels, a semiconductor switching device having a control terminal and first and second output terminals, said first output terminal being operatively connected to said source of said first voltage level, said second output terminal being connected to said source of said second voltage level, said control terminal being operatively connected to said input port, and said first output terminal being connected to said output port, and means responsive to the signal level at said output port to bias the other output terminal of said first semiconductor switching device towards said first voltage level.
Claim 19
Dependent Claim
114 words
In a self-biasing logic circuit having an input port, an output port and a source of first and second reference voltage levels, a semiconductor switching device having a control terminal and first and second output terminals, said first output terminal being operatively connected to said source of said first voltage level, said second output terminal being connected to said source of said second voltage level, said control terminal being operatively connected to said input port, and said first output terminal being connected to said output port, and means responsive to the signal level at said output port to bias the other output terminal of said first semiconductor switching device towards said first voltage level.
Claim 20
Dependent Claim
63 words
The logic circuit of claim 16, wherein said input port is adapted to receive signals at first and second logic levels corresponding to said first and second voltage levels, respectively, and further comprising a semiconductor load device connected between said first output terminal of said switching device and a source of said first voltage level, whereby said logic circuit functions as an inverter.
References Cited (Backward Citations)
US3255364A
Cited
US3296547A
Cited
US3392341A
Cited
US3483398A
Cited
US3523284A
Cited
US3500062A
Cited
US3513365A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-18 | 1976-01-17 | 1976-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-18 | 1980-01-17 | 1980-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-18 | 1984-01-17 | 1984-07-18 | $7700.00 | Window Closed / Lapsed |