Patent US4264829A successfully refreshed from Google Patents.
US4264829A
Expired / Lapsed
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MOS Inverter-buffer circuit having a small input capacitance
Assignee: Individual
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Filing: 1979-05-17
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Granted: 1981-04-28
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Expires: 1999-05-17
Abstract
Abstract For preventing an input signal supplied to an input terminal (A) from directly affecting an inverted signal derived at a node (15), an inverter stage of an inverter-buffer circuit composed of MOS transistors comprises two additional partial inverter stages (Q 6 -Q 5 and Q 7 -Q 8 ) between a buffer stage (Q 3 -Q 4 ) and a conventional inverter stage (Q 1 -Q 2 ) that serves now as an input-side partial inverter stage. The buffer stage favorably comprises an additional MOS transistor (Q 9 ) having a gate connected directly to the node in order to achieve a short switching delay.
Inventors
- 👤 Tetsuo Misaizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:07
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
359 words
In a circuit comprising an inverter stage between a signal input terminal and a first and a second intermediate terminal and between a power supply terminal and a point of a common potential and a buffer stage between said intermediate terminals and a signal output terminal and between said power supply terminal and said common potential point, said inverter stage including a first insulated-gate field-effect transistor of the enhancement type having a gate connected to said input terminal and operatively coupled to said first intermediate terminal, a source connected to said common potential point, and a drain connected to a node operatively coupled, in turn, to said second intermediate terminal and a second insulated-gate field-effect transistor of the depletion type having a gate connected to said node, a source connected also to said node, and a drain connected to said power supply terminal, said buffer stage comprising a third insulated-gate field-effect transistor of the enhancement type having a gate connected to said first intermediate terminal, a source connected to said common potential point, and a drain connected to said output terminal and a fourth insulated-gate field-effect transistor of the enhancement type having a gate connected to said second intermediate terminal, a source connected to said output terminal, and a drain connected to said power supply terminal, the improvement wherein said inverter stage comprises a fifth insulated-gate field-effect transistor of the depletion type having a gate connected to said input terminal, a source connected to said first intermediate terminal, and a drain connected to said power supply terminal, a sixth insulated-gate field-effect transistor of the enhancement type having a gate connected to said node, a source connected to said common potential point, and a drain connected to said first intermediate terminal, a seventh insulated-gate field-effect transistor of the enhancement type having a gate connected to said first intermediate terminal, a source connected to said common potential point, and a drain connected to said second intermediate terminal, and an eighth insulated-gate field-effect transistor of the depletion type having a gate connected to said node, a source connected to said second intermediate terminal, and a drain connected to said power supply terminal.
Claim 2
Dependent Claim
359 words
In a circuit comprising an inverter stage between a signal input terminal and a first and a second intermediate terminal and between a power supply terminal and a point of a common potential and a buffer stage between said intermediate terminals and a signal output terminal and between said power supply terminal and said common potential point, said inverter stage including a first insulated-gate field-effect transistor of the enhancement type having a gate connected to said input terminal and operatively coupled to said first intermediate terminal, a source connected to said common potential point, and a drain connected to a node operatively coupled, in turn, to said second intermediate terminal and a second insulated-gate field-effect transistor of the depletion type having a gate connected to said node, a source connected also to said node, and a drain connected to said power supply terminal, said buffer stage comprising a third insulated-gate field-effect transistor of the enhancement type having a gate connected to said first intermediate terminal, a source connected to said common potential point, and a drain connected to said output terminal and a fourth insulated-gate field-effect transistor of the enhancement type having a gate connected to said second intermediate terminal, a source connected to said output terminal, and a drain connected to said power supply terminal, the improvement wherein said inverter stage comprises a fifth insulated-gate field-effect transistor of the depletion type having a gate connected to said input terminal, a source connected to said first intermediate terminal, and a drain connected to said power supply terminal, a sixth insulated-gate field-effect transistor of the enhancement type having a gate connected to said node, a source connected to said common potential point, and a drain connected to said first intermediate terminal, a seventh insulated-gate field-effect transistor of the enhancement type having a gate connected to said first intermediate terminal, a source connected to said common potential point, and a drain connected to said second intermediate terminal, and an eighth insulated-gate field-effect transistor of the depletion type having a gate connected to said node, a source connected to said second intermediate terminal, and a drain connected to said power supply terminal.
Claim 3
Dependent Claim
45 words
The circuit as claimed in claim 1, wherein said buffer stage further comprises a ninth insulated-gate field-effect transistor of the enhancement type having a gate connected to said node, a source connected to said output terminal, and a drain connected to said power supply terminal.
Claim 4
Dependent Claim
24 words
The circuit as claimed in claim 1 or 2, wherein the size of said fifth transistor is smaller than that of said third transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-04-27 | 1984-10-27 | 1985-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-04-27 | 1988-10-27 | 1989-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-04-27 | 1992-10-27 | 1993-04-28 | $7700.00 | Window Closed / Lapsed |