Patent US2972742A successfully refreshed from Google Patents.
US3937983A
Expired / Lapsed
US
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Mos buffer circuit
Assignee: Intel Corp
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Filing: 1975-04-03
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Granted: 1976-02-10
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Expires: 1995-04-03
Abstract
Abstract An MOS dynamic buffer circuit described in terms of an inverter and used for inverting a timing signal is disclosed. Through the use of bootstrapping, the output from the inverter is equal to the voltage used to drive the inverter without having conduction through the output transistor when the inverter is not supplying an output signal. Thus, the inverter does not require the large amounts of standby power associated with prior art circuits.
Inventors
- 👤 John A. Reed
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:51
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
166 words
An MOS control circuit for controlling an output signal, said control circuit being coupled to a source of potential comprising: an output MOS device coupled to the output of said circuit and to said source of potential, said MOS device including a gate; a first circuit means for providing a first signal to said gate of said MOS device, said first circuit means including capacitance means; a second circuit means for providing a second signal to said gate of said MOS device, said second signal following said first signal and having a magnitude greater than said source of potential; and a third circuit means for electrically decoupling said capacitance means of said first circuit means from said gate of said MOS device as said second signal increases in magnitude so as to allow said second signal to increase in magnitude without restraint of said capacitance means of said first circuit means; whereby said output signal may have a magnitude substantially equal to said source of potential.
Claim 2
Dependent Claim
166 words
An MOS control circuit for controlling an output signal, said control circuit being coupled to a source of potential comprising: an output MOS device coupled to the output of said circuit and to said source of potential, said MOS device including a gate; a first circuit means for providing a first signal to said gate of said MOS device, said first circuit means including capacitance means; a second circuit means for providing a second signal to said gate of said MOS device, said second signal following said first signal and having a magnitude greater than said source of potential; and a third circuit means for electrically decoupling said capacitance means of said first circuit means from said gate of said MOS device as said second signal increases in magnitude so as to allow said second signal to increase in magnitude without restraint of said capacitance means of said first circuit means; whereby said output signal may have a magnitude substantially equal to said source of potential.
Claim 3
Dependent Claim
177 words
An MOS control circuit for causing an output signal to approach the voltage of a source of potential comprising: an output MOS device having a gate and two terminals, said one of said terminals being coupled to said source of potential and said other terminal to the output of said control circuit; a first MOS circuit means for applying a first voltage to said gate of said output MOS device, coupled to said output MOS device, said first MOS circuit means including capacitance means; a second MOS circuit for applying a second voltage to said gate of said output MOS device, coupled to said output MOS device, said second voltage having a magnitude greater than said source of potential; feedback means, for feeding back said output signal such as to cause said second voltage to be applied to said gate of said output MOS device and to electrically decouple said capacitance means of said first MOS circuit from said gate; whereby said output MOS device is first driven by said first voltage, then by said second voltage.
Claim 4
Dependent Claim
177 words
An MOS control circuit for causing an output signal to approach the voltage of a source of potential comprising: an output MOS device having a gate and two terminals, said one of said terminals being coupled to said source of potential and said other terminal to the output of said control circuit; a first MOS circuit means for applying a first voltage to said gate of said output MOS device, coupled to said output MOS device, said first MOS circuit means including capacitance means; a second MOS circuit for applying a second voltage to said gate of said output MOS device, coupled to said output MOS device, said second voltage having a magnitude greater than said source of potential; feedback means, for feeding back said output signal such as to cause said second voltage to be applied to said gate of said output MOS device and to electrically decouple said capacitance means of said first MOS circuit from said gate; whereby said output MOS device is first driven by said first voltage, then by said second voltage.
Claim 5
Dependent Claim
16 words
The circuit defined in claim 2 wherein said first MOS circuit means includes a bootstrap circuit.
Claim 6
Dependent Claim
16 words
The circuit defined in claim 2 wherein said second MOS circuit means includes a bootstrap circuit.
Claim 7
Dependent Claim
22 words
The circuit defined in claim 2 wherein said feedback means includes an MOS device having its gate coupled to said output signal.
Claim 8
Dependent Claim
18 words
The circuit defined in claim 2 wherein said circuit comprises n-channel MOS devices which utilize polycrystalline silicon gates.
Claim 9
Dependent Claim
151 words
A MOS control circuit having an input line for controlling an output line, said circuit being powered from a source of potential comprising: an output MOS device having a gate and at least two terminals, one of said terminals coupled to said source of potential and said other terminal coupled to said output line for coupling said potential to said output line; a second MOS device; a first bootstrap circuit means for generating a voltage greater than said source of potential coupled between said input line and said second MOS device; a second bootstrap circuit means for generating a voltage greater than said source of potential coupled between said output MOS device and said second MOS device; and feedback means for feeding back at least a portion of said output to said second MOS device; whereby an output signal may be generated which is approximately equal to said source of potential.
Claim 10
Dependent Claim
151 words
A MOS control circuit having an input line for controlling an output line, said circuit being powered from a source of potential comprising: an output MOS device having a gate and at least two terminals, one of said terminals coupled to said source of potential and said other terminal coupled to said output line for coupling said potential to said output line; a second MOS device; a first bootstrap circuit means for generating a voltage greater than said source of potential coupled between said input line and said second MOS device; a second bootstrap circuit means for generating a voltage greater than said source of potential coupled between said output MOS device and said second MOS device; and feedback means for feeding back at least a portion of said output to said second MOS device; whereby an output signal may be generated which is approximately equal to said source of potential.
Claim 11
Dependent Claim
22 words
The circuit defined in claim 7 wherein said feedback means includes an MOS device having its gate coupled to said output line.
Claim 12
Dependent Claim
20 words
The circuit defined in claim 8 wherein said circuit comprises n-channel MOS field effect transistors which employ polycrystalline silicon gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-02-09 | 1979-08-11 | 1980-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-02-09 | 1983-08-11 | 1984-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-02-09 | 1987-08-11 | 1988-02-10 | $7700.00 | Window Closed / Lapsed |