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US4233524A
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Multi-function logic circuit
Assignee: National Semiconductor Corp
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Filing: 1978-07-24
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Granted: 1980-11-11
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Expires: 1998-07-24
Abstract
Abstract Disclosed are multi-function logic circuits which simultaneously receive data signals and control signals. The control signals select logic operations for the multi-function logic circuits to perform on the data signals. Output logic signals, representing the result of the selected logical operation, are generated by the circuits. A four transistor embodiment selectively performs an EXCLUSIVE OR, OR, and NAND operation. A six transistor embodiment selectively performs a FULL ADD, NOR, OR NAND, and AND operation. The six transistor embodiment is suitable for use as an arithmetic logic unit in a digital computer.
Inventors
- 👤 Edward J. Burdick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:52
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/215; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
192 words
A multi-function logic circuit for simultaneously receiving data logic signals and control logic signals for performing selectable logical operations on said data logic signals in response to said control logic signals, and for generating output logic signals representing the result of said logical operation, comprising: first, second, third, and fourth switching means, each of said switching means having an input terminal, an output terminal, and a control terminal for switching data logic signals applied to said input terminal to said output terminal in response to control logic signals applied to said control terminal, said input terminals and said control terminals of said first and second switching means being cross-coupled together and coupled to respective input leads for receiving said data logic signals, said output terminals of said first and second switching means being coupled respectively to said input terminals of said third and fourth switching means, said output terminals of said third and fourth switching means being coupled to an output lead for generating said output logic signals thereon, and said control terminals of said third and fourth switching means being coupled to respective control leads for receiving said control logic signals.
Claim 2
Dependent Claim
192 words
A multi-function logic circuit for simultaneously receiving data logic signals and control logic signals for performing selectable logical operations on said data logic signals in response to said control logic signals, and for generating output logic signals representing the result of said logical operation, comprising: first, second, third, and fourth switching means, each of said switching means having an input terminal, an output terminal, and a control terminal for switching data logic signals applied to said input terminal to said output terminal in response to control logic signals applied to said control terminal, said input terminals and said control terminals of said first and second switching means being cross-coupled together and coupled to respective input leads for receiving said data logic signals, said output terminals of said first and second switching means being coupled respectively to said input terminals of said third and fourth switching means, said output terminals of said third and fourth switching means being coupled to an output lead for generating said output logic signals thereon, and said control terminals of said third and fourth switching means being coupled to respective control leads for receiving said control logic signals.
Claim 3
Dependent Claim
20 words
A logic circuit according to claim 1, wherein each of said switching means is a single MOS Field Effect transistor.
Claim 4
Dependent Claim
18 words
A logic circuit according to claim 1, wherein each of said switching means is a single bipolar transistor.
Claim 5
Dependent Claim
18 words
A logic circuit according to claim 1, wherein said logic circuit is integrated on a single semiconductor chip.
Claim 6
Dependent Claim
104 words
A logic circuit according to claim 1, and further comprising: fifth and sixth switching means, each of which is identical in construction to said first through fourth switching means, said input terminals and said control terminals of said fifth and sixth switching means being cross-coupled together, said input terminal of said fifth switching means being coupled to said output lead, said input terminal of said sixth switching means being coupled to an input lead for said control logic signals, and said output terminals of said fifth and sixth switching means being coupled to a second output lead for generating second output logic signals thereon.
Claim 7
Dependent Claim
20 words
A logic circuit according to claim 5, wherein each of said switching means is a single MOS Field Effect transistor.
Claim 8
Dependent Claim
18 words
A logic circuit according to claim 5, wherein each of said switching means is a single bipolar transistor.
Claim 9
Dependent Claim
18 words
A logic circuit according to claim 5, wherein said logic circuit is integrated on a single semiconductor chip.
Claim 10
Dependent Claim
23 words
A logic circuit according to claim 5, wherein said second output lead is coupled to a second voltage source through a resistive load.
Claim 11
Dependent Claim
21 words
A logic circuit according to claim 1, wherein said output lead is coupled to a voltage source through a resistive load.
Claim 12
Dependent Claim
34 words
A logic circuit according to claims 10 or 9 wherein the resistive load is an MOS Field Effect transistor having a source, a drain and a gate, said gate being coupled to said source.
References Cited (Backward Citations)
US3413488A
Cited
US3460132A
Cited
US3602732A
Cited
US3666968A
Cited
US3668425A
Cited
US3683202A
Cited
US3691401A
Cited
US3980897A
Cited
US3965367A
Cited
US4006365A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-11 | 1984-05-12 | 1984-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-11 | 1988-05-12 | 1988-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-11 | 1992-05-12 | 1992-11-11 | $7700.00 | Window Closed / Lapsed |