US3668425A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Complementary metal oxide semiconductor exclusive or gate
Assignee: Motorola Solutions Inc
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Filing: 1970-12-28
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Granted: 1972-06-06
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Expires: 1990-12-28
Abstract
Abstract A complementary metal oxide semiconductor (CMOS) exclusive OR gate is shown having a minimum number of devices for performing the exclusive OR function. The exclusive OR function is performed by utilizing the normal two input signals as logic indicating signals and generating a control signal which is a complement of one of the two logic signals. A different configuration results with the selection of the logic signal from which the control signal is to be generated. The capacitance of the output node or output signal is charged by any one of a plurality of current paths associated with each logic configuration.
Inventors
- 👤 Bernard H Schmidt Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:21
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/215
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
309 words
A CMOS exclusive OR circuit comprising: a source of potential having a first voltage level and a second voltage level and said second voltage level being more negative than said first voltage level; a first input logic terminal and a second input logic terminal; a first logic signal applied to said first terminal and a second logic signal applied to said second terminal; an output terminal; a first current charging and discharging path including said output terminal; a first N-channel, enhancement mode, MOSFET having source, drain, gate, and substrate terminals and said gate terminal being responsive to said first logic signal and said drain terminal being connected to said output terminal; a second N-channel enhancement mode, MOSFET having source, drain, gate, and substrate terminals and having said drain terminal of said second N-channel MOSFET connected to the source terminal of said first N-channel MOSFET and said source of said second N-channel MOSFET connected to said second voltage level; said substrate terminal of said first N-channel MOSFET being connected to said substrate terminal of said second N-channel MOSFET and both being connected to said second voltage level; said gate terminal of said second N-channel MOSFET being responsive to said second logic signal; a second charging and discharging path comprising a first P-channel enhancement mode MOSFET having source, drain, gate, and substrate terminals and having said source terminal connected to said output terminal, and said drain terminal connected to said first input logic signal terminal and said gate terminal being responsive to said second input logic signaL, and said substrate terminal being connected to said first voltage level; and said first logic signal being at said first voltage level and said second logic signal being at said second voltage level, whereby said first P-channel MOSFET is activated for forming a charging path from said first input terminal to said output terminal.
Claim 2
Dependent Claim
309 words
A CMOS exclusive OR circuit comprising: a source of potential having a first voltage level and a second voltage level and said second voltage level being more negative than said first voltage level; a first input logic terminal and a second input logic terminal; a first logic signal applied to said first terminal and a second logic signal applied to said second terminal; an output terminal; a first current charging and discharging path including said output terminal; a first N-channel, enhancement mode, MOSFET having source, drain, gate, and substrate terminals and said gate terminal being responsive to said first logic signal and said drain terminal being connected to said output terminal; a second N-channel enhancement mode, MOSFET having source, drain, gate, and substrate terminals and having said drain terminal of said second N-channel MOSFET connected to the source terminal of said first N-channel MOSFET and said source of said second N-channel MOSFET connected to said second voltage level; said substrate terminal of said first N-channel MOSFET being connected to said substrate terminal of said second N-channel MOSFET and both being connected to said second voltage level; said gate terminal of said second N-channel MOSFET being responsive to said second logic signal; a second charging and discharging path comprising a first P-channel enhancement mode MOSFET having source, drain, gate, and substrate terminals and having said source terminal connected to said output terminal, and said drain terminal connected to said first input logic signal terminal and said gate terminal being responsive to said second input logic signaL, and said substrate terminal being connected to said first voltage level; and said first logic signal being at said first voltage level and said second logic signal being at said second voltage level, whereby said first P-channel MOSFET is activated for forming a charging path from said first input terminal to said output terminal.
Claim 3
Dependent Claim
34 words
A CMOS exclusive OR circuit as recited in claim 1, and further comprising: a capacitive device connected to said output terminal for being charged to said voltage level of said first input logic signal.
Claim 4
Dependent Claim
139 words
A CMOS exclusive OR circuit as recited in claim 1, and further comprising: a control signal being the complement of one of said logic signals; a third charging and discharging path comprising a third N-channel, enhancement mode MOSFET having source, drain, gate and substrate terminals and said source terminal being connected to said drain terminal of said first P-channel MOSFET, and said drain terminal being connected to said output terminal, and said substrate terminal being connected to said second voltage level, and said gate terminal being responsive to said complement signal of said second logic signal; and said first logic signal being at said first voltage level and said second logic signal being at said second voltage level, whereby said first P-channel MOSFET is activated for forming a charging path from said first input terminal to said output terminal.
Claim 5
Dependent Claim
34 words
A CMOS exclusive OR circuit as recited in claim 3, and further comprising: a capacitive device connected to said output terminal for being charged to said voltage level of said first input logic signal.
Claim 6
Dependent Claim
37 words
A CMOS exclusive OR circuit as recited in claim 4, wherein: said third N-channel MOSFET being activated by said complement signal of said second logic input signal for forming a parallel current with said first P-channel MOSFET.
Claim 7
Dependent Claim
54 words
A CMOS exclusive OR circuit as recited in claim 3, wherein: said first logic signal being at said second voltage level, whereby: said first P-channel MOSFET and said third N-channel MOSFET are simultaneously activated for sharing said current in said third charging and discharging path from said first input terminal to said output terminal.
Claim 8
Dependent Claim
31 words
A CMOS exclusive OR circuit as recited in claim 6, and further comprising: a capacitive device connected to said output terminal for being discharged to a plurality of second voltage levels.
Claim 9
Dependent Claim
194 words
A CMOS exclusive OR circuit as recited in claim 1, and further comprising: a control signal being the complement of one of said logic signals; a third charging and discharging path comprising a second P-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and said drain terminal being connected to said second logic signal input terminal, and said gate terminal being connected to said first logic signal input terminal, and said substrate terminal being connected to said first voltage level and said source terminal being connected to said output terminal; a third N-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and said source terminal being connected to said second logic signal input terminal, and said drain terminal being connected to said output terminal, and said substrate terminal being connected to said second voltage level, and said gate terminal being connected to said complement signal of said first logic signal; and said first logic signal being now at said second voltage level, whereby; said second P-channel MOSFET and said third N-channel MOSFET are activated for forming a discharging path from said output terminal to said second logic signal input terminal.
Claim 10
Dependent Claim
33 words
A CMOS exclusive OR circuit as recited in claim 8, and further comprising: a capacitive device connected to said output terminal for discharging to the voltage level of said second input logic signal.
Claim 11
Dependent Claim
21 words
A CMOS exclusive OR circuit as recited in claim 8, wherein: said second logic signal being at said first voltage level.
Claim 12
Dependent Claim
33 words
A CMOS exclusive OR circuit as recited in claim 8, and further comprising: a capacitive device connected to said output terminal for charging to the voltage level of said second input logic signal.
Claim 13
Dependent Claim
53 words
A CMOS exclusive OR circuit as recited in claim 9, and further comprising: a fourth charging path comprising; said first P-channel MOSFET being activated and forming a discharging path to said first input logic level terminal from said output terminal whereby said capacitive device is discharged to a plurality of second voltage levels.
Claim 14
Dependent Claim
118 words
A CMOS exclusive OR circuit as recited in claim 3, and further comprising: a fourth charging and discharging path comprising; a second P-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and having its drain terminal connected to said second logic signal input terminal, and having its source electrode connected to said output signal output terminal, and having its substrate terminal connected to said first voltage level, and having its gate terminal connected to said first logic signal input terminal; and said first logic signal now being at said second voltage level, whereby said second P-channel MOSFET being activated for forming said sixth discharging path between said second logic signal input terminal and said output terminal.
Claim 15
Dependent Claim
33 words
A CMOS exclusive OR circuit as recited in claim 13, and further comprising: a capacitive device connected to said output terminal for discharging to the voltage level of said second input logic signal.
Claim 16
Dependent Claim
42 words
A CMOS exclusive OR circuit as recited in claim 13 wherein: said second logic signal being at said first voltage level; and said complement of said second logic signal being at said second voltage level for turning off said third N-Channel MOSFET.
Claim 17
Dependent Claim
33 words
A CMOS exclusive OR circuit as recited in claim 15, and further comprising: a capacitive device connected to said output terminal for charging to said voltage level of said second input logic signal.
Claim 18
Dependent Claim
169 words
A CMOS exclusive OR circuit as recited in claim 8, wherein said complement signal of said first logic signal being generated by an inverter circuit formed integral therewith, said inverter circuit comprising: a third P-channel, enhancement mode, MOSFET having source, drain, gate, and substrate terminals and said source terminal being connected to said first voltage level, and said gate terminal being connected to said first logic signal input terminal and said substrate terminal being connected to said first voltage level; and a fourth N-channel, enhancement mode, MOSFET having source, drain, gate, and substrate terminals, and said drain terminal being connected to a junction formed by said drain terminal of said third P-channel MOSFET and said gate terminal of said third N-channel MOSFET and said substrate terminal being connected to said drain terminal and both being connected to said second voltage level, and said gate terminal being connected to said first logic signal input terminal whereby; said complement signal of said first logic signal is available at said first junction.
Claim 19
Dependent Claim
174 words
A CMOS exclusive OR circuit as recited in claim 13, wherein said complement signal of said second logic signal being generated by an inverter circuit formed integral therewith, said inverter circuit comprising: a third P-channel, enhancement mode, MOSFET, having source, drain, gate and substrate terminals and said source terminal being connected to said first voltage level, and said gate terminal being connected to said second logic signal input terminal, and said substrate terminal being connected to said first voltage level; and a fourth N-channel, enhancement mode MOSFET having source, drain, gate and substrate terminals, and said drain terminal being connected to a second jUnction formed by said drain terminal of said third P-channel MOSFET and said gate terminal of said third N-channel MOSFET, and said substrate terminal being connected to said source terminal of said same MOSFET and both being connected to said second voltage level, and said gate terminal being connected to said second logic signal input terminal, whereby; said complement signal of said second logic signal is available at said second junction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |