Low level pulse polarity detector

Claim 2

A low level pulse polarity detector, comprising: first, second, third and fourth NAND circuits, each having an output terminal and first and second input terminals; first and second capacitors, each having first and second terminals; means for coupling said first and second capacitors'' first terminals across a signal source; means for directly intercoupling the first input terminals of said first and fourth NAND circuits and the output terminals of said first and third NAND circuits to said first capacitor''s second terminal; means for directly intercoupling the first input terminals of said second and third NAND circuits and the output terminals of said secoNd the fourth NAND circuits to said second capacitor''s second terminal; means for directly intercoupling the second input terminals of said third and fourth NAND circuits; means for directly intercoupling the second input terminals of said first and second NAND circuits; means for directly intercoupling the second terminals of said first and second capacitors to an output means; means for sensing the relative signal level of said first or second capacitor''s second terminal at said output means.

Claim 3

A low level pulse polarity detector, comprising: first, second, third and fourth NAND circuits, each having an output terminal and first and second input terminals; means for coupling first and second nodes across a signal source; means for directly intercoupling the first input terminals of said first and fourth NAND circuits and the output terminals of said first and third NAND circuits to said first node; means for directly intercoupling the first input terminals of said second and third NAND circuits and the output terminals of said second and fourth NAND circuits to said second node; means for directly intercoupling the second input terminal of said third and fourth NAND circuits; means for directly intercoupling the second input terminals of said first and second NAND circuits; means directly intercoupling said first and second nodes to an output means for sensing the state of said third or fourth NAND circuit as a function of the relative polarity of an input signal coupled across said first and second nodes.

Claim 4

A low level pulse polarity detector, comprising: first, second, third and fourth NAND circuits, each having an output terminal and first and second input terminals; means for coupling first and second nodes across a signal source; means for directly intercoupling the first input terminals of said first and fourth NAND circuits and the output terminals of said first and third NAND circuits to said first node; means for directly intercoupling the first input terminals of said second and third NAND circuits and the output terminals of said second and fourth NAND circuits to said second node; means for directly intercoupling the second input terminal of said third and fourth NAND circuits; means for directly intercoupling the second input terminals of said first and second NAND circuits; means directly intercoupling said first and second nodes to an output means for sensing the state of said third or fourth NAND circuit as a function of the relative polarity of an input signal coupled across said first and second nodes.

Claim 5

A low level pulse polarity detector, comprising: first, second, third, fourth, fifth and sixth NAND circuits, each having an output terminal and first and second input terminals; first and second capacitors, each having first and second terminals; means for coupling said first and second capacitors'' first terminals across a signal source; means for directly intercoupling the first input terminals of said first, fourth and fifth NAND circuits and the output terminals of said first and third NAND circuit to said first capacitors'' second terminal; means for directly intercoupling the first input terminals of said second, third and sixth NAND circuits and the output terminals of said second and fourth NAND circuits to said second capacitors'' second terminal; means for directly intercoupling the second input terminal of said third and fourth NAND circuits to a sample terminal; means for directly intercoupling the second input terminals of said first and second NAND circuits to an initiate terminal; means for directly intercoupling the output terminals of said fifth and sixth NAND circuits to a data out terminal; means coupling the second input terminal of said fifth NAND circuit to a normal strobe terminal; means coupling the second input terminal of said sixth NAND circuit to a complement strobe terminal.

Claim 6

A low level pulse polarity detector, comprising: first, second, third, fourth, fifth and sixth NAND circuits, each having an output terminal and first and second input terminals; first and second capacitors, each having first and second terminals; means for coupling said first and second capacitors'' first terminals across a signal source; means for directly intercoupling the first input terminals of said first, fourth and fifth NAND circuits and the output terminals of said first and third NAND circuit to said first capacitors'' second terminal; means for directly intercoupling the first input terminals of said second, third and sixth NAND circuits and the output terminals of said second and fourth NAND circuits to said second capacitors'' second terminal; means for directly intercoupling the second input terminal of said third and fourth NAND circuits to a sample terminal; means for directly intercoupling the second input terminals of said first and second NAND circuits to an initiate terminal; means for directly intercoupling the output terminals of said fifth and sixth NAND circuits to a data out terminal; means coupling the second input terminal of said fifth NAND circuit to a normal strobe terminal; means coupling the second input terminal of said sixth NAND circuit to a complement strobe terminal.

Claim 7

A low level pulse polarity detector, comprising: first and second substantially similar latching circuits, each having an output terminal and first and second input terminals; first and second substantially similar feedback circuits, each having an output terminal and first and second input terminals; first and second separate electrical nodes which serve as both input and output terminals across which an input signal is coupled and at which an output signal is detected; means for directly intercoupling the first input terminals of said first feedback circuit and said second latching circuit and the output terminals of said first feedback circuit and said first latching circuit to said first node; means for directly intercoupling the first input terminals of said second feedback circuit and said first latching circuit and the output terminals of said second feedback circuit and said second latching circuit to said second node; means for directly intercoupling the second Input terminals of said first and second latching circuits to a sample signal terminal; means for directly intercoupling the second input terminals of said first and second feedback circuits to an initiate signal terminal; and, input means for coupling an input signal across said input terminals for latching said first and second latching circuits ON and OFF or OFF and ON, respectively, as a function of the relative input signal level across said first and second nodes.

Claim 8

A low level pulse polarity detector, comprising: first and second substantially similar latching circuits, each having an output terminal and first and second input terminals; first and second substantially similar feedback circuits, each having an output terminal and first and second input terminals; first and second separate electrical nodes which serve as both input and output terminals across which an input signal is coupled and at which an output signal is detected; means for directly intercoupling the first input terminals of said first feedback circuit and said second latching circuit and the output terminals of said first feedback circuit and said first latching circuit to said first node; means for directly intercoupling the first input terminals of said second feedback circuit and said first latching circuit and the output terminals of said second feedback circuit and said second latching circuit to said second node; means for directly intercoupling the second Input terminals of said first and second latching circuits to a sample signal terminal; means for directly intercoupling the second input terminals of said first and second feedback circuits to an initiate signal terminal; and, input means for coupling an input signal across said input terminals for latching said first and second latching circuits ON and OFF or OFF and ON, respectively, as a function of the relative input signal level across said first and second nodes.

Claim 9

The detector of claim 4 in which said latching circuits and said feedback circuits are substantially similar diode-transistor logic NAND circuits.

Claim 10

The detector of claim 5 in which all said circuitry is formed on a single integrated circuit chip.

Claim 11

The detector of claim 4 in which said input means includes first and second capacitors for serially coupling said input signal across said first and second input terminals, respectively.

Claim 12

The detector of claim 4 further including: first and second substantially similar strobe circuits, each having an output terminal and first and second input terminals; means for directly intercoupling the first input terminal of said first strobe circuit to said first node; means for directly intercoupling the first input terminal of said second strobe circuit to said second node; and, strobe means coupled to the second input terminals of said first and second strobe circuits for providing on their output terminals signals that are representative of the states of said first and second latching circuits.

Claim 13

The detector of claim 4 further including: an initiate terminal directly coupled to the directly intercoupled second input terminals of said first and second feedback circuits for receiving an initiate signal turning said first and second feedback circuits OFF; and, a sample terminal directly coupled to the directly intercoupled second input terminals of said first and second latching circuits for receiving a sample signal and latching said first and second latching circuits ON and OFF or OFF and ON, respectively, as a function of the relative input signal level across said first and second nodes while said initiate signal is concurrently coupled to said initiate terminal.