US3553491A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for sensing binary signals from a high-speed memory device
Assignee: International Business Machines Corp
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Filing: 1969-01-10
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Granted: 1971-01-05
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Expires: 1989-01-10
Abstract
Abstract A high-speed memory device sensing circuit comprises a difference amplifier having outputs connected to threshold circuit means which detects positive going voltage signals. Outputs from the threshold circuits are connected to set a pair of latches when positive going signals are detected by the threshold circuits. Means for detecting the order in which the latches are set comprises a NAND gate and a third latch connected to the output thereof which is set to produce an output signal when a binary one is read out of memory and which remains in the reset condition when a binary zero signal is read out of memory.
Inventors
- 👤 Raymond A Schulz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 03:10
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/2893; H03K3/2897; H03K5/00; H03K5/156; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
97 words
A circuit arrangement for sensing input signals representing binary ones and zeros including: a difference amplifier having a first output line and a second output line; threshold circuit means for detecting a predetermined positive voltage level on said first and second output lines; bistable circuit means switchable in sequence by said threshold circuit means in response to positive voltages above said predetermined voltage on said first and second output lines; and means for determining the sequence of switching of said bistable circuit means as an indication of the existence of a binary one or zero input signal.
Claim 2
Dependent Claim
97 words
A circuit arrangement for sensing input signals representing binary ones and zeros including: a difference amplifier having a first output line and a second output line; threshold circuit means for detecting a predetermined positive voltage level on said first and second output lines; bistable circuit means switchable in sequence by said threshold circuit means in response to positive voltages above said predetermined voltage on said first and second output lines; and means for determining the sequence of switching of said bistable circuit means as an indication of the existence of a binary one or zero input signal.
Claim 3
Dependent Claim
35 words
A circuit arrangement in accordance with claim 1 in which said bistable circuit means comprises latch means operable to generate a sequence of output signals in response to switching pulses from said threshold circuit means.
Claim 4
Dependent Claim
56 words
A circuit arrangement in accordance with claim 2 in which said bistable circuit means comprises a first and second latch means, said latch means being connected to said threshold means to be set in a sequence, and said sequence determining means comprises circuitry for determining the order of setting of said first and second latch means.
Claim 5
Dependent Claim
80 words
A circuit arrangement in accordance with claim 3 in which said sequence determining means comprises a gate circuit means operable to generate a signal in response to a first sequence of setting of said first and second latch means and to generate no signal in response to a second sequence of setting of said latch means; and circuit means operable in response to said gate circuit means output signal switchable to indicate said first sequence of operation of said latches.
Claim 6
Dependent Claim
29 words
A circuit arrangement in accordance with claim 4 in which said sequence determining means comprises a bistable latch circuit settable to a predetermined condition by said gate circuit means.
Claim 7
Dependent Claim
68 words
A circuit arrangement in accordance with claim 5 in which said threshold circuit means comprises first and second threshold circuits connected to said first and second outputs of said difference amplifier means and operable to generate output set signals to said first and second latch means in response to positive going signals above a predetermined voltage level on said first and second outputs of said difference amplifier means.
Claim 8
Dependent Claim
28 words
A circuit arrangement in accordance wIth claim 6 in which said threshold circuit means comprises first and second threshold circuits connected to share a common voltage level generator.
References Cited (Backward Citations)
US3466471A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-04 | 1974-07-06 | 1975-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-04 | 1978-07-06 | 1979-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-04 | 1982-07-06 | 1983-01-05 | $7700.00 | Window Closed / Lapsed |