High yield processing for silicon-on-sapphire CMOS integrated circuits

Claim 1

A method for fabricating a semiconductor device on a semiconductor substrate supported by an insulating sapphire substrate, comprising the steps of: forming at least two silicon regions separated by an insulating region having a substantially planar upper surface; forming a first masking structure such that the surface of said first silicon region is exposed at a first and second area and is masked at a third area and the surface of said second silicon region is exposed at a fourth and fifth area and is masked at a sixth area, doping said first and second areas of said first silicon region with a first conductivity; doping said fourth and fifth areas of said second silicon region with a second conductivity; oxidizing said first, second, fourth, and fifth areas of said first and second silicon regions to form a thick field oxide; removing said first masking structure; locating a concentration of dopant in the silicon substrate near the silicon-sapphire interface, beneath said third area of the first silicon region; oxidizing said third and sixth areas of said first and second silicon regions to form an oxide; forming metal connections to said first, second, fourth, and fifth areas; and forming a conductive layer overlaying the oxide covering said third and sixth areas.

Claim 2

A method for fabricating a semiconductor device on a semiconductor substrate supported by an insulating sapphire substrate, comprising the steps of: forming at least two silicon regions separated by an insulating region having a substantially planar upper surface; forming a first masking structure such that the surface of said first silicon region is exposed at a first and second area and is masked at a third area and the surface of said second silicon region is exposed at a fourth and fifth area and is masked at a sixth area, doping said first and second areas of said first silicon region with a first conductivity; doping said fourth and fifth areas of said second silicon region with a second conductivity; oxidizing said first, second, fourth, and fifth areas of said first and second silicon regions to form a thick field oxide; removing said first masking structure; locating a concentration of dopant in the silicon substrate near the silicon-sapphire interface, beneath said third area of the first silicon region; oxidizing said third and sixth areas of said first and second silicon regions to form an oxide; forming metal connections to said first, second, fourth, and fifth areas; and forming a conductive layer overlaying the oxide covering said third and sixth areas.

Claim 3

A method for fabricating a semiconductor device on a semiconductor substrate supported by an insulating substrate, comprising the steps of: forming at least two silicon regions separated by an insulating region having a substantially planar upper surface; forming a first masking structure such that the surface of said first silicon region is exposed at a first and second area and is masked at a third area and the surface of said second silicon region is exposed at a fourth and fifth area and is masked at a sixth area; doping said first and second areas of said first silicon region with a first conductivity; doping said fourth and fifth areas of said second silicon region with a second conductivity; oxidizing said first, second, fourth, and fifth areas of said first and second silicon regions to form a thick field oxide; removing said first masking structure; locating a concentration of dopant in the silicon substrate near the silicon-insulating substrate interface, beneath said third area of the first silicon region; oxidizing said third and sixth areas of said first and second silicon regions to form an oxide; forming metal connections to said first, second, fourth, and fifth areas; and forming a conductive layer overlaying the oxide covering said third and sixth area.

Claim 4

A method for fabricating a semiconductor device on a semiconductor substrate supported by an insulating substrate, comprising the steps of: forming at least two silicon regions separated by an insulating region having a substantially planar upper surface; forming a first masking structure such that the surface of said first silicon region is exposed at a first and second area and is masked at a third area and the surface of said second silicon region is exposed at a fourth and fifth area and is masked at a sixth area; doping said first and second areas of said first silicon region with a first conductivity; doping said fourth and fifth areas of said second silicon region with a second conductivity; oxidizing said first, second, fourth, and fifth areas of said first and second silicon regions to form a thick field oxide; removing said first masking structure; locating a concentration of dopant in the silicon substrate near the silicon-insulating substrate interface, beneath said third area of the first silicon region; oxidizing said third and sixth areas of said first and second silicon regions to form an oxide; forming metal connections to said first, second, fourth, and fifth areas; and forming a conductive layer overlaying the oxide covering said third and sixth area.

Claim 9

A method for fabricating a semiconductor device on at least two spaced apart semiconductor regions supported by a dielectrically insulating sapphire substrate comprising the steps of: forming a first masking layer on the surface of a silicon semiconductor layer on said substrate and a second masking layer on the surface of said first masking layer; selectively removing portions of said second and first masking layers so as to expose portions of said semiconductor layer; thermally oxidizing said exposed portions of said semiconductor layer, so as to form at least two spaced apart semiconductor regions; forming a third masking layer; forming a fourth masking layer on the surface of said third masking layer; selectively removing portions of said third and fourth masking layers so as to expose first and second areas and to mask a third area on said first semiconductor region; selectively removing portions of said third and fourth masking layers so as to expose a fourth and fifth area and to mask a sixth area on said second semiconductor region; doping said first and second regions with a first conductivity; doping said fourth and fifth regions with a second conductivity; oxidizing said first, second, fourth, and fifth regions; removing said fourth masking layer; forming a fifth masking layer to mask an ion implantation, said fifth masking layer exposing said third area on said first semiconductor region and ion implanting a concentration of dopant in said first semiconductor region beneath said third area near the silicon-sapphire interface; removing said fifth masking layer; oxidizing said third and sixth areas to form an oxide; forming metal connections with said first, second, fourth, and fifth areas; and forming a conductive layer overlaying the oxide covering said third and sixth areas.

Claim 10

A method for fabricating a semiconductor device on at least two spaced apart semiconductor regions supported by a dielectrically insulating sapphire substrate comprising the steps of: forming a first masking layer on the surface of a silicon semiconductor layer on said substrate and a second masking layer on the surface of said first masking layer; selectively removing portions of said second and first masking layers so as to expose portions of said semiconductor layer; thermally oxidizing said exposed portions of said semiconductor layer, so as to form at least two spaced apart semiconductor regions; forming a third masking layer; forming a fourth masking layer on the surface of said third masking layer; selectively removing portions of said third and fourth masking layers so as to expose first and second areas and to mask a third area on said first semiconductor region; selectively removing portions of said third and fourth masking layers so as to expose a fourth and fifth area and to mask a sixth area on said second semiconductor region; doping said first and second regions with a first conductivity; doping said fourth and fifth regions with a second conductivity; oxidizing said first, second, fourth, and fifth regions; removing said fourth masking layer; forming a fifth masking layer to mask an ion implantation, said fifth masking layer exposing said third area on said first semiconductor region and ion implanting a concentration of dopant in said first semiconductor region beneath said third area near the silicon-sapphire interface; removing said fifth masking layer; oxidizing said third and sixth areas to form an oxide; forming metal connections with said first, second, fourth, and fifth areas; and forming a conductive layer overlaying the oxide covering said third and sixth areas.

Claim 11

A method for obtaining substantially correct registration between two or more semiconductor devices on a semiconductor substrate comprising the steps of: forming a masking structure such that first and second areas on said semiconductor substrate are exposed, and a third area on said semiconductor substrate is masked; doping said first and second areas with a first conductivity; oxidizing said first and second areas on said semiconductor substrate to form an oxide over said first and second areas; removing said first masking structure; oxidizing said third area to form an oxide; forming metal connections to said first and second areas; and forming a conductive layer overlaying the oxide covering said third area.

Claim 12

A method for obtaining substantially correct registration between two or more semiconductor devices on a semiconductor substrate comprising the steps of: forming a masking structure such that first and second areas on said semiconductor substrate are exposed, and a third area on said semiconductor substrate is masked; doping said first and second areas with a first conductivity; oxidizing said first and second areas on said semiconductor substrate to form an oxide over said first and second areas; removing said first masking structure; oxidizing said third area to form an oxide; forming metal connections to said first and second areas; and forming a conductive layer overlaying the oxide covering said third area.

Claim 13

A method for pseudo self-aligning the gate oxide of a semiconductor device so as to reduce the overlap of the gate oxide with the adjacent doped regions, comprising the steps of: forming a first masking structure on a semiconductor substrate which exposes a first and second area and masks a third area on said semiconductor substrate; growing a thick oxide at said first and second areas; removing said first masking structure; growing a gate oxide over said third area; forming metal connections to said first and second areas; and forming a conductive layer overlaying said oxide covering said third area.

Claim 14

A method for pseudo self-aligning the gate oxide of a semiconductor device so as to reduce the overlap of the gate oxide with the adjacent doped regions, comprising the steps of: forming a first masking structure on a semiconductor substrate which exposes a first and second area and masks a third area on said semiconductor substrate; growing a thick oxide at said first and second areas; removing said first masking structure; growing a gate oxide over said third area; forming metal connections to said first and second areas; and forming a conductive layer overlaying said oxide covering said third area.

Claim 16

A method for fabricating a semiconductor device on at least two spaced apart semiconductor regions supported by a dielectrically insulating substrate comprising the steps of: forming a first masking layer on the surface of a silicon semiconductor layer on said substrate and a second masking layer on the surface of said first masking layer; selectively removing portions of said second and first masking layers so as to expose portions of said semiconductor layer; thermally oxidizing said exposed portions of said semiconductor layer, so as to form at least two spaced apart semiconductor regions; forming a third masking layer; forming a fourth masking layer on the surface of said third masking layer; selectively removing portions of said third and fourth masking layers so as to expose first and second areas and to mask a third area on said first semiconductor region; selectively removing portions of said third and fourth masking layers so as to expose a fourth and fifth area and to mask a sixth area on said second semiconductor region; doping said first and second regions with a first conductivity; doping said fourth and fifth regions with a second conductivity; oxidizing said first, second, fourth, and fifth regions, removing said fourth masking layer; forming a fifth masking layer to mask an ion implantation, said fifth masking layer exposing said third area on said first semiconductor region and ion implanting a concentration of dopant in said first semiconductor region beneath said third area near the silicon-insulating substrate interface; removing said fifth masking layer; oxidizing said third and sixth areas to form an oxide; forming metal connections with said first, second, fourth, and fifth areas; and forming a conductive layer overlaying the oxide covering said third and sixth areas.

Claim 17

A method for fabricating a semiconductor device on at least two spaced apart semiconductor regions supported by a dielectrically insulating substrate comprising the steps of: forming a first masking layer on the surface of a silicon semiconductor layer on said substrate and a second masking layer on the surface of said first masking layer; selectively removing portions of said second and first masking layers so as to expose portions of said semiconductor layer; thermally oxidizing said exposed portions of said semiconductor layer, so as to form at least two spaced apart semiconductor regions; forming a third masking layer; forming a fourth masking layer on the surface of said third masking layer; selectively removing portions of said third and fourth masking layers so as to expose first and second areas and to mask a third area on said first semiconductor region; selectively removing portions of said third and fourth masking layers so as to expose a fourth and fifth area and to mask a sixth area on said second semiconductor region; doping said first and second regions with a first conductivity; doping said fourth and fifth regions with a second conductivity; oxidizing said first, second, fourth, and fifth regions, removing said fourth masking layer; forming a fifth masking layer to mask an ion implantation, said fifth masking layer exposing said third area on said first semiconductor region and ion implanting a concentration of dopant in said first semiconductor region beneath said third area near the silicon-insulating substrate interface; removing said fifth masking layer; oxidizing said third and sixth areas to form an oxide; forming metal connections with said first, second, fourth, and fifth areas; and forming a conductive layer overlaying the oxide covering said third and sixth areas.