US3865653A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit having a switching transistor and a load transistor, in particular for a semiconductor storage element
Assignee: Individual
•
Filing: 1974-01-02
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Granted: 1975-02-11
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Expires: 1994-01-02
Abstract
Abstract A logic circuit having a switching transistor and a load transistor constructed in accordance with complementary channel thin-film techniques wherein the switching transistor is produced by a double-diffusion process and the load transistor of the complementary type is produced during the process steps in the production of the switching transistor.
Inventors
- 👤 Karl Goser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 03:42
CPC Classifications
H; H10; H10D; H10D86/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H10D86/01; H10D86/03; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/053; Y10S148/085; Y10S148/106
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
148 words
A METHOD FOR PRODUCING A LOGIC CIRCUIT INCLUDING A SWITCHING TRANSISTOR AND A LOAD TRANSISTOR IN COMPLEMENTARY CHANNEL THIN LAYER TECHNIQUE CONNECTED TO SAID SWITCHING TRANSISTOR, COMPRISING THE STEPS OF, MASKING A SEMICONDUCTOR LAYER OF A FIRST CONDUCTIVITY TYPE WHICH OVERLIES A HIGH OHMIC SUBSTRATE TO EXPOSE ZONES FOR DIFFUSION, DIFFUSING AN OPPOSITE CONDUCTIVITY MATERIAL THROUGH SAID OPENINGS INTO THE DIFFUSION ZONES AND UNDER THE EDGES OF THE OPENINGS TO PRODUCE DOPED ZONES OF THE SWITCHING AND OF THE LOAD TRANSISTORS, MASKING AGAIN BY COVERING SOME OF THE OPENINGS AND PROVIDING AN ADDITIONAL OPENING TO DEFINE A FURTHER ZONE OF THE SWITCHING TRANSISTOR, DIFFUSING MATERIAL OF THE FIRST CONDUCTIVITY TYPE THROUGH SAID OPENING AND CONTEMPORANEOUSLY LIMITING ADVANCEMENT OF THE DIFFUSION IN ONE OF THE PREVIOUSLY DIFFUSED ZONES SO THAT A PORTION OF THE PREVIOUSLY DIFFUSED ZONE REMAINS, REMOVING THE MASKING, AND APPLYING ELECTRICAL CONTACTS TO THE DIFFUSED ZONES.
Claim 2
Independent Claim
148 words
A METHOD FOR PRODUCING A LOGIC CIRCUIT INCLUDING A SWITCHING TRANSISTOR AND A LOAD TRANSISTOR IN COMPLEMENTARY CHANNEL THIN LAYER TECHNIQUE CONNECTED TO SAID SWITCHING TRANSISTOR, COMPRISING THE STEPS OF, MASKING A SEMICONDUCTOR LAYER OF A FIRST CONDUCTIVITY TYPE WHICH OVERLIES A HIGH OHMIC SUBSTRATE TO EXPOSE ZONES FOR DIFFUSION, DIFFUSING AN OPPOSITE CONDUCTIVITY MATERIAL THROUGH SAID OPENINGS INTO THE DIFFUSION ZONES AND UNDER THE EDGES OF THE OPENINGS TO PRODUCE DOPED ZONES OF THE SWITCHING AND OF THE LOAD TRANSISTORS, MASKING AGAIN BY COVERING SOME OF THE OPENINGS AND PROVIDING AN ADDITIONAL OPENING TO DEFINE A FURTHER ZONE OF THE SWITCHING TRANSISTOR, DIFFUSING MATERIAL OF THE FIRST CONDUCTIVITY TYPE THROUGH SAID OPENING AND CONTEMPORANEOUSLY LIMITING ADVANCEMENT OF THE DIFFUSION IN ONE OF THE PREVIOUSLY DIFFUSED ZONES SO THAT A PORTION OF THE PREVIOUSLY DIFFUSED ZONE REMAINS, REMOVING THE MASKING, AND APPLYING ELECTRICAL CONTACTS TO THE DIFFUSED ZONES.
Claim 3
Dependent Claim
49 words
The method set forth in claim 1, wherein the second step of masking is further defined as providing a nitride layer over the specified openings to prevent the growth of an oxide coating; and the step of removing the masks is further defined by etching away the nitride layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-10 | 1978-08-12 | 1979-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-10 | 1982-08-12 | 1983-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-10 | 1986-08-12 | 1987-02-11 | $7700.00 | Window Closed / Lapsed |