Patent US4151010A successfully refreshed from Google Patents.
US4151010A
Expired / Lapsed
US
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Forming adjacent impurity regions in a semiconductor by oxide masking
Assignee: International Business Machines Corp
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Filing: 1978-06-30
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Granted: 1979-04-24
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Expires: 1998-06-30
Abstract
Abstract A method for forming adjacent impurity regions of differing conductivities in a semiconductor substrate without using lithography. N type impurities of a first conductivity are introduced into the substrate to form first impurity regions. The substrate is then oxidized to create a mask having a thickness which is greater over the N type impurity regions than over the remainder of the substrate. A portion of the masking layer is then removed, preferably by dip-etching, to a depth which is sufficient to re-expose the substrate only. Impurities of a second conductivity are then introduced in the substrate adjacent the N type impurity regions, with the remaining portion of the mask protecting the N type impurity regions from introduction of the second impurities therein.
Inventors
- 👤 George R. Goth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:56
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/65; H10P14/6502; H10P30/00; H10P30/20; H10P30/22; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; H10P76/00; H10P76/40; Y; Y10; Y10S; Y10S438/00; Y10S438/911
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
113 words
A method for introducing impurities into a region adjacent a first N type impurity region in a silicon semiconductor substrate, said adjacent region being either a N type region of lower impurity level or a P type region, comprising the steps of: oxidizing said substrate to create a mask having a thickness which is greater over said first impurity region than over said adjacent region; removing a portion of said masking layer sufficient to re-expose said adjacent region, but leaving a remainder to protect said first impurity region; and introducing said impurities into said adjacent region, said first impurity region being protected from the introduction of said impurities by said remaining masking layer.
Claim 2
Independent Claim
113 words
A method for introducing impurities into a region adjacent a first N type impurity region in a silicon semiconductor substrate, said adjacent region being either a N type region of lower impurity level or a P type region, comprising the steps of: oxidizing said substrate to create a mask having a thickness which is greater over said first impurity region than over said adjacent region; removing a portion of said masking layer sufficient to re-expose said adjacent region, but leaving a remainder to protect said first impurity region; and introducing said impurities into said adjacent region, said first impurity region being protected from the introduction of said impurities by said remaining masking layer.
Claim 3
Dependent Claim
21 words
A method as in claim 1 wherein said removal step is accomplished by etching said oxide layer in buffered hydrofluoric acid.
Claim 4
Dependent Claim
15 words
A method as in claim 1 wherein said removal step is accomplished by dry etching.
Claim 5
Dependent Claim
22 words
A method as in claim 1 wherein said step of introducing impurities into said adjacent region is accomplished by a diffusion process.
Claim 6
Dependent Claim
31 words
A method as in claim 4 wherein: said N type impurities are selected from the group consisting of arsenic and phosphorus; and said impurities diffused into said adjacent region are boron.
Claim 7
Dependent Claim
20 words
A method as in claim 1 wherein said step of introducing impurities into said adjacent region is by ion implantation.
Claim 8
Dependent Claim
14 words
A method as in claim 1 wherein said oxidizing step is accomplished in steam.
Claim 9
Independent Claim
122 words
A method for forming adjacent subcollector and isolation regions of a transistor comprising the steps of: introducing impurities of N+ conductivity into a silicon semiconductor substrate having a lower impurity level to form said subcollector region; oxidizing said substrate to create a mask having a thickness which is greater over said subcollector region than over at least a portion of said substrate which is adjacent said subcollector region; removing a portion of said masking layer sufficient to re-expose said substrate portion, but leaving a remainder to protect said subcollector region; and introducing P type impurities into said substrate portion to form said isolation region, said subcollector region being protected from the introduction of said P type impurities by said remaining masking layer.
Claim 10
Independent Claim
122 words
A method for forming adjacent subcollector and isolation regions of a transistor comprising the steps of: introducing impurities of N+ conductivity into a silicon semiconductor substrate having a lower impurity level to form said subcollector region; oxidizing said substrate to create a mask having a thickness which is greater over said subcollector region than over at least a portion of said substrate which is adjacent said subcollector region; removing a portion of said masking layer sufficient to re-expose said substrate portion, but leaving a remainder to protect said subcollector region; and introducing P type impurities into said substrate portion to form said isolation region, said subcollector region being protected from the introduction of said P type impurities by said remaining masking layer.
Claim 11
Dependent Claim
21 words
A method as in claim 8 wherein said removal step is accomplished by etching said oxide layer in buffered hydrofluoric acid.
Claim 12
Dependent Claim
15 words
A method as in claim 8 wherein said removal step is accomplished by dry etching.
Claim 13
Dependent Claim
33 words
A method as in claim 8 wherein said substrate is of P-type conductivity; and said subcollector region exhibits a surface impurity concentration of greater than around 10 20 atoms per cm 3 .
Claim 14
Dependent Claim
24 words
A method as in claim 8 wherein said step of introducing said N+ impurities is accomplished by a diffusion or an ion implantation process.
Claim 15
Dependent Claim
21 words
A method as in claim 8 wherein said step of introducing said P type impurities is accomplished by a diffusion process.
Claim 16
Dependent Claim
22 words
A method as in claim 8 wherein said oxidizing step is accomplished in steam at around 1000° C. for around one hour.
Claim 17
Independent Claim
158 words
A method for forming adjacent base and collector regions of a lateral PNP transistor comprising the steps of: introducing impurities of N type conductivity into a selected region of a section of a silicon semiconductor substrate to form said base region; introducing impurities of P type conductivity into said base region to form an emitter region; said substrate section having a lower impurity level than that of said base and emitter regions; oxidizing said substrate to create a mask having a thickness which is greater over said base and emitter regions than over said substrate section; removing a portion of said masking layer sufficient to re-expose said substrate section, but leaving a remainder to protect said base and emitter regions; and introducing P type impurities into said substrate section to form a collector region of said PNP transistor, said base and emitter regions being protected from the introduction of said P type impurities by said remaining masking layer.
Claim 18
Independent Claim
158 words
A method for forming adjacent base and collector regions of a lateral PNP transistor comprising the steps of: introducing impurities of N type conductivity into a selected region of a section of a silicon semiconductor substrate to form said base region; introducing impurities of P type conductivity into said base region to form an emitter region; said substrate section having a lower impurity level than that of said base and emitter regions; oxidizing said substrate to create a mask having a thickness which is greater over said base and emitter regions than over said substrate section; removing a portion of said masking layer sufficient to re-expose said substrate section, but leaving a remainder to protect said base and emitter regions; and introducing P type impurities into said substrate section to form a collector region of said PNP transistor, said base and emitter regions being protected from the introduction of said P type impurities by said remaining masking layer.
Claim 19
Dependent Claim
21 words
A method as in claim 15 wherein said removal step is accomplished by etching said oxide layer in buffered hydrofluoric acid.
Claim 20
Dependent Claim
15 words
A method as in claim 15 wherein said removal step is accomplished by dry etching.
Claim 21
Dependent Claim
28 words
A method as in claim 15 wherein: said base region impurities are phosphorus; and said oxidizing step is accomplished in steam at between 700° C. and 900° C.
Claim 22
Dependent Claim
20 words
A method as in claim 15 wherein said step of introducing said collector impurities is accomplished by a diffusion process.
Claim 23
Independent Claim
122 words
A method for forming a tunnel diode comprising the steps of: introducing impurities of N+ conductivity into a a selected region of a section of a silicon semiconductor substrate having a lower impurity level to form a degenerately-doped N+ type impurity region; oxidizing said substrate to create a mask having a thickness which is greater over said N + type region than over said substrate section; removing a portion of said masking layer sufficient to re-expose said substrate section, but leaving a remainder to protect said N+ region; introducing impurities of a P+ conductivity into said substrate section to form a degenerately-doped P type region, said N+ region being protected from the introduction of said second impurity by said remaining masking layer.
Claim 24
Independent Claim
122 words
A method for forming a tunnel diode comprising the steps of: introducing impurities of N+ conductivity into a a selected region of a section of a silicon semiconductor substrate having a lower impurity level to form a degenerately-doped N+ type impurity region; oxidizing said substrate to create a mask having a thickness which is greater over said N + type region than over said substrate section; removing a portion of said masking layer sufficient to re-expose said substrate section, but leaving a remainder to protect said N+ region; introducing impurities of a P+ conductivity into said substrate section to form a degenerately-doped P type region, said N+ region being protected from the introduction of said second impurity by said remaining masking layer.
Claim 25
Dependent Claim
21 words
A method as in claim 1 wherein said removal step is accomplished by etching said oxide layer in buffered hydrofluoric acid.
Claim 26
Dependent Claim
15 words
A method as in claim 21 wherein said removal step is accomplished by dry etching.
Claim 27
Dependent Claim
45 words
A method as in claim 21 wherein: said N+ impurity region comprises arsenic exhibiting a surface concentration of around 3×10 20 atoms per cm 3 ; and said P+ impurity region comprises boron exhibiting a surface concentration of around 5×10 19 per cm 3 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-23 | 1982-10-23 | 1983-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-23 | 1986-10-23 | 1987-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-23 | 1990-10-23 | 1991-04-24 | $7700.00 | Window Closed / Lapsed |