Patent US4141135A successfully refreshed from Google Patents.
US4141135A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor process using lapped substrate and lapped low resistivity semiconductor carrier
Assignee: Thales SA
•
Filing: 1976-10-12
•
Granted: 1979-02-27
•
Expires: 1996-10-12
Abstract
Abstract A process intended for avoiding the "flip chip bonding" technique, well known for planar diodes, is provided. It is further applicable to mesa diodes and planar transistors. It comprises an essential step: the lapping of the substrate up to reduce its thickness to the same order of magnitude as the upper active layer of a semiconductor device, thus facilitating the cooling of the device through the substrate towards a heat sink. This essential step is made possible by virtue of a preliminary bonding on the upper layer of the semiconductor device of a block of silicon. According to a first alternative of the invention the block is finally eliminated and the device is a conventional one with a very thin substrate. According to a second alternative of the invention, the block is retained and lapped after addition of the heat sink, then metalized to provide a secondary way to the thermal flux.
Inventors
- 👤 Raymond Henry
- 👤 Jean-Victor Bouvet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:20
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/10; H10D; H10D62/00; H10D62/10; H10D62/117; H10W44/00; H10W44/20; H10W76/00; H10W76/10; H10W76/12; H10W76/13; H10W76/132; H10W72/00; H10W72/50; H10W72/59
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
124 words
A process for producing semiconductor devices of planar diode type, with a very low thermal resistance, starting from a wafer consisting of a substrate, at least one active layer of semiconductor material exhibiting electrodes and a metal coating, said process comprising the following steps: (a) bonding of a block of low resistivity semiconductor material onto said active part; (b) lapping of said substrate; (c) finishing the device according to the following sub-steps: (c 1 ) depositing a first layer of highly heat conductive metal onto the lapped substrate; (c 2 ) depositing a second layer of low resistivity metal onto said first layer; (c 3 ) lapping of the block; (c 4 ) metallising the lapped block surface by a highly heat conductive metal.
Claim 2
Dependent Claim
124 words
A process for producing semiconductor devices of planar diode type, with a very low thermal resistance, starting from a wafer consisting of a substrate, at least one active layer of semiconductor material exhibiting electrodes and a metal coating, said process comprising the following steps: (a) bonding of a block of low resistivity semiconductor material onto said active part; (b) lapping of said substrate; (c) finishing the device according to the following sub-steps: (c 1 ) depositing a first layer of highly heat conductive metal onto the lapped substrate; (c 2 ) depositing a second layer of low resistivity metal onto said first layer; (c 3 ) lapping of the block; (c 4 ) metallising the lapped block surface by a highly heat conductive metal.
Claim 3
Dependent Claim
156 words
A process for producing semiconductor devices of mesa diode type with a very low thermal resistance, starting from a wafer consisting of a substrate supporting mesa diode structures protected by a passivation layer except at the tops of the mesa structures whereon a metallic coating is deposited, said process comprising the following steps: (a) depositing a thick layer of glass between said mesa structures filling the gaps between said structures and laying bare said metal coatings; (b) bonding of a block of low resistivity semiconductor material onto said metal coatings; (c) lapping of said substrate; (d) finishing the device according to the following sub-steps: (d 1 ) depositing a first layer of highly heat conductive metal onto the lapped substrate; (d 2 ) depositing a second layer of low resistivity metal onto said first layer; (d 3 ) lapping of the block; (d 4 ) metallising the lapped block surface by a highly heat conductive metal.
Claim 4
Dependent Claim
156 words
A process for producing semiconductor devices of mesa diode type with a very low thermal resistance, starting from a wafer consisting of a substrate supporting mesa diode structures protected by a passivation layer except at the tops of the mesa structures whereon a metallic coating is deposited, said process comprising the following steps: (a) depositing a thick layer of glass between said mesa structures filling the gaps between said structures and laying bare said metal coatings; (b) bonding of a block of low resistivity semiconductor material onto said metal coatings; (c) lapping of said substrate; (d) finishing the device according to the following sub-steps: (d 1 ) depositing a first layer of highly heat conductive metal onto the lapped substrate; (d 2 ) depositing a second layer of low resistivity metal onto said first layer; (d 3 ) lapping of the block; (d 4 ) metallising the lapped block surface by a highly heat conductive metal.
Claim 5
Dependent Claim
165 words
A process for producing semiconductor devices of transistor type, with a very low thermal resistance, starting from a transistor device comprising a substrate, interleaved emitter and base regions and finger shaped metallisations in contact with said regions and leading respectively to a common emitter stump and to a common base stump, said process comprising the following steps: (a) depositing a layer of insulating material onto said finger shaped metallisations; (b) forming windows in said layer, laying bare said emitter fingers; (b) bonding a block of low resistivity semiconductor material onto said metallisation, partially covering said finger shaped metallisations; (d) lapping of said substrate; (e) finishing of the device according to the following sub-steps: (e 1 ) depositing a first layer of highly conductive metal onto the lapped substrate; (e 2 ) depositing a second layer of low resistivity metal onto the first layer; (e 3 ) lapping of the block; (e 4 ) metallising of the lapped block surface by a highly heat conductive metal.
Claim 6
Dependent Claim
165 words
A process for producing semiconductor devices of transistor type, with a very low thermal resistance, starting from a transistor device comprising a substrate, interleaved emitter and base regions and finger shaped metallisations in contact with said regions and leading respectively to a common emitter stump and to a common base stump, said process comprising the following steps: (a) depositing a layer of insulating material onto said finger shaped metallisations; (b) forming windows in said layer, laying bare said emitter fingers; (b) bonding a block of low resistivity semiconductor material onto said metallisation, partially covering said finger shaped metallisations; (d) lapping of said substrate; (e) finishing of the device according to the following sub-steps: (e 1 ) depositing a first layer of highly conductive metal onto the lapped substrate; (e 2 ) depositing a second layer of low resistivity metal onto the first layer; (e 3 ) lapping of the block; (e 4 ) metallising of the lapped block surface by a highly heat conductive metal.
References Cited (Backward Citations)
GB807728A
Cited
GB863119A
Cited
GB992963A
Cited
GB1120488A
Cited
US3445303A
Cited
GB1126338A
Cited
US3343255A
Cited
US3559282A
Cited
GB1281010A
Cited
US3609474A
Cited
GB1295892A
Cited
US3775200A
Cited
US3689993A
Cited
US3908187A
Cited
FR2232081B1
Cited
US4035830A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-26 | 1982-08-28 | 1983-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-26 | 1986-08-28 | 1987-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-26 | 1990-08-28 | 1991-02-27 | $7700.00 | Window Closed / Lapsed |