High voltage power transistor and method for making

Claim 2

A COMPOSITE SEMICONDUCTOR STRUCTUE CONSTITUTING A PLURALITY OF POWER TRANSISTORS COMPRISING: A. A JUNCTION WATER OF MONOCRYSTALLICE SILICON CONTAINING IN STACKED RELATION AN OUTER COLLECTOR LAYER OF RELATIVELY LOW RESISTIVITY AND DEFINING THE BOTTOM MAJOR FACE OF SAID JUNCTION WAFER, AN INNER COLLECTOR LAYER OF RELATIVELY HIGH RESISTIVITY SURMOUNTING SAID COLLECTOR LAYER, A BASE LAYER SURMOUNTING SAID INNER COLLECTOR LAYER AND DEFINING THEREWITH BASE COLLETOR P/N JUNCTION, AND DEFINING WITH THE EMITTER REGIONS ON SAIDBASELAYER THE TOP MAJOR FACE OF EXPOSED SURFACE OF SAID BLAYER THE TOP MAJOR FACE OF SAID JUNCTION WAFER, B. A SILICON CARRIER FOR SUPPORTING AND REINFORCING SAID JUNCTION WAFER, C. MENAS FORMING A METALLIC ALLOY BOND BETWEEN THE BOTTOM MAJOR FACE OF THE JUNCTIO WAFER AND THE TOP MAJOR FACE OF THE CARRIER WAFER, HEREIN THE CARRIER WAFER AND THE METALLIC ALLOY BOND ARE SUBSTANTIALLY COEXTENSIVE WITH THE JUNCTION WAFER AND THE BOTTOM MAJOR FACE OF SAID CARRIER WAFER IS COVERED IN ITS ENTIRETY BY A METALLIC COLLECTOR CONTACT LAYER IN OBMIC CONTACT THEREWITH. D. MEANS FORMING A POURALITY OF GROOVES IN THE TOP MAJOR FACE OF THE JUNCTION WAFER, BETWEEN THE IMITTER REGIONS THEREOF, AND HAVING A DEPTH ESTENDING PART WAY THROUGH SAID OUTER COLLECTOU LABER, SAID GROOVES DEFINING MESAS IN SAID JUNCTION WAFER WITH EACH OF SAID MESAS INCLUDING A PORTION OF SAID OUTER COLLECTOR LAYER SURMOUNTED BY A PORTION OF SAID INNER COLLECTOR LAYER TOPPED BY A PORTION OF SAID BASE LAYER AND AN EMITTER REGION THEREON, E. AND A COATING OF GLASS PASSIVATING MATERIAL ON THE SIDE WALLS AND BOTTOM OF SAID GROOVES COVERING THE EXPOSED EDGES OF THE INTERFACES BETWEEN THE BASE AND INNER COLLECTOR REGIONS IN EACH MESA AND THE INNER COLLECTOR REGION AND OUTER COLLECTER REGION IN EACH MESA, WHEREBY SAID BONDED WAFERS CAN BE DIVIDED INTO INDIVIDUAL TRANSISTOR PELLETS AT SEPARATION FACES EXTENDING GENERALLY NORMAL TO THE MAJOR OF SAID WAFERS ALONG THE BOTTOM OF SAID GROOVES.

Claim 3

A composite semiconductor structure constituting a plurality of power transistors comprising: a. a junction wafer of monocrystalline silicon containing in stacked relation an outer collector layer of relatively low resistivity and defining the bottom major face of said junction wafer, an inner collector layer of relatively high resistivity surmounting said collector layer, a base layer surmounting said inner collector layer and defining therewith a base collector P/N junction, and an array of spaced emitter regions on said base layer and defining with the exposed surface of said base layer the top major face of said junction wafer, b. a silicon carrier wafer for supporting and reinforcing said junction wafer, c. means forming an aluminum alloy bond between the bottom major face of the junction wafer and the top major face of the carrier wafer wherein the carrier wafer and the aluminum alloy bond are substantially coextensive with the junction wafer and the bottom major face of said carrier wafer is covered in its entirety by a metallic collector contact layer in ohmic contact therewith, and wherein a layer of aluminum remains between said wafers, d. means forming a plurality of grooves in the top major face of the junction wafer, between the emitter regions thereof, and having a depth extending part way through said outer collector layer, said grooves defining mesas in said junction wafer with each of said mesas including a portion of said outer collector layer surmounted by a portion of said inner collector layer topped by a portion of said base layer and an emitter region thereon, e. and a coating of glass passivating material on the side walls and bottoms of said grooves covering the exposed edges of the interfaces between the base and inner collector region in each mesa and the inner collector region and outer collector region in each mesa, whereby said bonded wafers can be subdivided into individual transistor pellets at separation faces extending generally normal to the major faces of said wafers along the bottom of said grooves.

Claim 4

A composite semiconductor structure constituting a plurality of power transistors comprising: a. a junction wafer of monocrystalline silicon containing in stacked relation an outer collector layer of relatively low resistivity and defining the bottom major face of said junction wafer, an inner collector layer of relatively high resistivity surmounting said collector layer, a base layer surmounting said inner collector layer and defining therewith a base collector P/N junction, and an array of spaced emitter regions on said base layer and defining with the exposed surface of said base layer the top major face of said junction wafer, b. a silicon carrier wafer for supporting and reinforcing said junction wafer, c. means forming an aluminum alloy bond between the bottom major face of the junction wafer and the top major face of the carrier wafer wherein the carrier wafer and the aluminum alloy bond are substantially coextensive with the junction wafer and the bottom major face of said carrier wafer is covered in its entirety by a metallic collector contact layer in ohmic contact therewith, and wherein a layer of aluminum remains between said wafers, d. means forming a plurality of grooves in the top major face of the junction wafer, between the emitter regions thereof, and having a depth extending part way through said outer collector layer, said grooves defining mesas in said junction wafer with each of said mesas including a portion of said outer collector layer surmounted by a portion of said inner collector layer topped by a portion of said base layer and an emitter region thereon, e. and a coating of glass passivating material on the side walls and bottoms of said grooves covering the exposed edges of the interfaces between the base and inner collector region in each mesa and the inner collector region and outer collector region in each mesa, whereby said bonded wafers can be subdivided into individual transistor pellets at separation faces extending generally normal to the major faces of said wafers along the bottom of said grooves.

Claim 5

A structure according to claim 2 wherein said carrier wafer is monocrystalline silicon of at least about 10 mils thickness and has a resistivity of about 0.001 ohm cm.