Microprogrammed computer employing a decode read only memory (DROM) and a microinstruction read only memory (ROM)

Claim 2

A microprogrammed computer comprising an instruction register for registering a machine instruction word; a decode read only memory connected to said instruction register for storing the start address data of microprogram routines which correspond to machine instruction words, respectively and the control bit data which correspond to the machine instruction words, respectively, said microprogram routines each consisting of a plurality of microinstructions; a control register for registering the control bit data, one at a time; a read only memory for storing the microinstructions of the microprogram routines; an address register for registering an address datum based on which a specified microinstruction is read out from the read only memory, said address register connected to the decode read only memory for receiving the start address data from said decode read only memory and also connected to the input of said read only memory; a data register for storing the microinstruction read out from the read only memory; first means for changing the function of the microinstruction stored in the data register in response to a specified control signal from the control register; and second means for feeding a specified address datum to the address register in preference to the start address data sent to the address register from the decode read only memory in response to a specified control signal from the control register, thereby changing the execution sequence to the microprograms in the read only memory.

Claim 3

A microprogrammed computer according to claim 1, wherein said first means comprises a plurality of general registers; an accumulator register for registering a first operand datum of an arithmetic/logic operation; an arithmetic logic unit for executing arithmetic and logical operations based on the outputs of the general registers and the accumulator register; bus means for supplying the output of the arithmetic logic unit; and an operation mode designation means for designating normally the mode of the operation to be executed in the arithmetic logic unit in accordance with the microinstruction stored in said data register and for designating, when said control register stores a control bit datum which instructs a change of function of microinstruction, a mode of operation different from the mode of operation designated according to the microinstruction stored in said data register.

Claim 4

A microprogrammed computer according to claim 2, wherein said operation mode designation means is constituted by a decoder circuit which designates one of operation modes in accordance with the output of said data register and the control signal from said control register.

Claim 5

A microprogrammed computer according to claim 2, further comprising an address register for storing a specified register datum from said data register and selecting, based on the register datum, one of said general registers.

Claim 6

A microprogrammed computer according to claim 1, wherein said second means comprises execution stage control means for controlling the execution stage of a microprogram in accordance with a specified control bit datum stored in said control register; address pattern generating means for generating in response to the specified control bit datum an address pattern representing the microprogram whose execution stage is to be changed; a clock pulse generator for generating timing signals to drive said address register and said data register, thereby to change the execution stage of a microprogram; and gate means for supplying a specified address datum to said address register under control of the control signals from said execution stage control means.

Claim 7

A microprogrammed computer according to claim 5, wherein said execution stage control means generates a first control signal to control the branch address of a branching instruction, a second control signal to control the start address of a microprogram routine from said decode read only memory, and a third control signal to control an address generated by said address pattern means, thereby to change the execution stage of the microprogram represented by the address pattern.

Claim 8

A microprogrammed computer according to claim 5, wherein said gate means is constituted by a plurality of gates corresponding to the control signals derived from the execution stage control means, and said gates includes at least three gates, a first gate to pass the branch address of a branch instruction, a second gate to pass the start address of a microprogram routine from said decode read only memory, and a third gate to pass an address generated by said address pattern generating means.

Claim 9

A microprogrammed computer according to claim 5, further comprising a program status word register which supplies a program status word to said execution stage control means and said address pattern generating means, thereby to change the execution stage of a microprogram.

Claim 10

A microprogrammed computer comprising an instruction register for registering a machine instruction word; a decode read only memory connected to said instruction register for storing the start address data of microprogram routines which correspond to machine instruction words, respectively and the control bit data which corresponds to the machine instruction words, respectively, said microprogram routines each consisting of a plurality of microinstructions; a control register for registering the control bit data, one at a time; a read only memory for storing the microinstructions of the microprogram routines; an address register for registering an address datum based on which a specified microinstruction is read out from the read only memory said address register connected to the input of said read only memory; a data register for registering the microinstruction read out from the read only memory; a plurality of general registers; an accumulator register for registering a first operand datum of an arithmetic/logic operation; an arithmetic logic unit for executing arithmetic and logical operations based on the outputs of the general registers and the accumulator register; a bus for supplying the output of the arithmetic logic unit; and an operation mode designation circuit for designating normally the mode of the operation to be executed in the arithmetic logic unit in accordance with the microinstruction stored in said data register and for designating, when said control register stores a control bit datum which instructs a change of function of microinstruction, a mode of operation different from the mode of operation designated according to the microinstruction stored in said data register.

Claim 11

A microprogrammed computer comprising an instruction register for registering a machine instruction word; a decode read only memory connected to said instruction register for storing the start address data of microprogram routines which correspond to machine instruction words, respectively and the control bit data which corresponds to the machine instruction words, respectively, said microprogram routines each consisting of a plurality of microinstructions; a control register for registering the control bit data, one at a time; a read only memory for storing the microinstructions of the microprogram routines; an address register for registering an address datum based on which a specified microinstruction is read out from the read only memory said address register connected to the input of said read only memory; a data register for registering the microinstruction read out from the read only memory; a plurality of general registers; an accumulator register for registering a first operand datum of an arithmetic/logic operation; an arithmetic logic unit for executing arithmetic and logical operations based on the outputs of the general registers and the accumulator register; a bus for supplying the output of the arithmetic logic unit; and an operation mode designation circuit for designating normally the mode of the operation to be executed in the arithmetic logic unit in accordance with the microinstruction stored in said data register and for designating, when said control register stores a control bit datum which instructs a change of function of microinstruction, a mode of operation different from the mode of operation designated according to the microinstruction stored in said data register.

Claim 12

A microprogrammed computer comprising an instruction register for registering a machine instruction word; a decode read only memory connected to said instruction register for storing the start address data of microprogram routines which correspond to machine instruction words, respectively and the control bit data which correspond to the machine instruction words, respectively, said microprogram routines each consisting of a plurality of microinstructions; a control register for storing the control bit data, one at a time; a read only memory for storing the microinstructions of the microprogram routines; an address register for registering an address datum based on which a specified microinstruction is read out from the read only memory, said address register connected to the input of said read only memory; a data register for registering the microinstruction read out from the read only memory; execution stage control means for controlling the execution stage of a microprogram in accordance with a specified control bit datum stored in said control register; an address pattern generating circuit for generating in response to the specified control bit datum an address pattern representing the microprogram whose execution stage is to be changed; a clock pulse generator controlled by the address pattern generating circuit for generating timing signals to drive said address register and said data register, thereby to change the execution stage of a microprogram; and a gate circuit for supplying a specified address datum to said address register under control of the control signals from said execution stage control means.

Claim 13

A microprogrammed computer comprising an instruction register for registering a machine instruction word; a decode read only memory connected to said instruction register for storing the start address data of microprogram routines which correspond to machine instruction words, respectively and the control bit data which correspond to the machine instruction words, respectively, said microprogram routines each consisting of a plurality of microinstructions; a control register for storing the control bit data, one at a time; a read only memory for storing the microinstructions of the microprogram routines; an address register for registering an address datum based on which a specified microinstruction is read out from the read only memory, said address register connected to the input of said read only memory; a data register for registering the microinstruction read out from the read only memory; execution stage control means for controlling the execution stage of a microprogram in accordance with a specified control bit datum stored in said control register; an address pattern generating circuit for generating in response to the specified control bit datum an address pattern representing the microprogram whose execution stage is to be changed; a clock pulse generator controlled by the address pattern generating circuit for generating timing signals to drive said address register and said data register, thereby to change the execution stage of a microprogram; and a gate circuit for supplying a specified address datum to said address register under control of the control signals from said execution stage control means.