US4058850A
Expired / Lapsed
US
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Programmable controller
Assignee: Xerox Corp
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Filing: 1974-08-12
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Granted: 1977-11-15
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Expires: 1994-08-12
Abstract
Abstract An improved programmable controller which includes a non-destructive memory program storage means wherein the controller is programmable by altering the program by substitution of the non-destructive memory storage means. The memory program storage means is comprised of a first memory portion which stores an operation program for the apparatus and a second memory portion which controls the sequence of execution of the operation program. The second memory portion can simultaneously address a location in the first memory portion and a location in an input-output data interface memory.
Inventors
- 👤 Sikander Sheikh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:48
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G03; G03G; G03G21/00; G03G21/14; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G05B2219/00; G05B2219/10; G05B2219/13; G05B2219/13012
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
154 words
A processor for controlling an apparatus by actuating elements of said apparatus in accordance with a predetermined program and in response to apparatus condition indicators comprising: a first non-destructive memory which stores an operational program including a multiplicity of instructions at predetermined locations for control of said apparatus; memory control means, including a second non-destructive memory coupled to said first non-destructive memory, for controlling a sequence of execution of program instructions stored in the first memory; a buffer memory interface for storing input data to said processor and for storing output data from said processor, said memory control means arranged for simultaneously addressing a memory location in said first memory and at least one location in said buffer memory interface; and, means for decoding a first memory instruction which is extracted from said first memory and for causing an execution of said first memory instruction as determined by an operation code of said instruction.
Claim 2
Dependent Claim
154 words
A processor for controlling an apparatus by actuating elements of said apparatus in accordance with a predetermined program and in response to apparatus condition indicators comprising: a first non-destructive memory which stores an operational program including a multiplicity of instructions at predetermined locations for control of said apparatus; memory control means, including a second non-destructive memory coupled to said first non-destructive memory, for controlling a sequence of execution of program instructions stored in the first memory; a buffer memory interface for storing input data to said processor and for storing output data from said processor, said memory control means arranged for simultaneously addressing a memory location in said first memory and at least one location in said buffer memory interface; and, means for decoding a first memory instruction which is extracted from said first memory and for causing an execution of said first memory instruction as determined by an operation code of said instruction.
Claim 3
Dependent Claim
28 words
The process of claim 1 wherein said memory control means provides for addressing a input data buffer memory interface location and an output data buffer memory interface location.
Claim 4
Dependent Claim
39 words
The processor of claim 2 wherein said first non-destructive memory includes instructions having stored data word having an address test field and wherein means are provided for directly addressing said input buffer interface location with said address test field.
Claim 5
Dependent Claim
40 words
The processor of claim 2 wherein said buffer memory interface includes an address port means, said input data buffer interface locations and said output data buffer interface locations being addressed by said memory control means through said address port means.
Claim 6
Dependent Claim
64 words
The processor of claim 2 including an auxiliary register, means for introducing data into said register, a comparator means, means for applying an address-test field of an addressed instruction word in said first memory and the contents of said register to said comparator for comparing information therein, and means for generating a control signal for use by said processor in accordance with the comparison.
Claim 7
Dependent Claim
36 words
The processor of claim 3 wherein said apparatus has a plurality of distinct operational states and data is entered into said input buffer memory locations which is indicative of the state of operation of the apparatus.
Claim 8
Dependent Claim
47 words
The process of claim 1 wherein said memory control means includes a counter for sequentially addressing the memory locations in said second memory, and means for coupling said counter to said buffer memory interface for simultaneously addressing said input buffer memory locations and output buffer memory locations.
Claim 9
Dependent Claim
40 words
The processor of claim 6 including an auxiliary read/write memory, means coupling an address test field to said auxiliary memory for addressing a memory location in said auxiliary memory and means for introducing data to said addressed auxiliary memory location.
Claim 10
Dependent Claim
55 words
The processor of claim 8 including a second auxiliary memory, means for coupling said first non-destructive memory to said second auxiliary memory for addressing said second auxiliary memory at a memory location for an introduction of data thereto, and means for coupling said address test field to said second auxiliary memory at an addressed location.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-11-14 | 1981-05-16 | 1981-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-11-14 | 1985-05-16 | 1985-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-11-14 | 1989-05-16 | 1989-11-15 | $7700.00 | Window Closed / Lapsed |