US3768076A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple peripheral coupled data processor system
Assignee: INF CO INT L
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Filing: 1972-04-12
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Granted: 1973-10-23
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Expires: 1992-04-12
Abstract
Abstract A digital data processor which receives instruction and operand words from an external store, operates on such words by execution of internal micro-instruction programmes and communicates with a plurality of peripheral units through a multi-coupling arrangement, comprises means executing the specific operations controlling exchanges between the processor and the peripheral units and the coupling units of the peripheral units comprise only means for the local control of operation of said peripheral units.
Inventors
- 👤 A Recoque
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:27
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
289 words
A digital data processing system for exchange operations between an external instruction and operand word external store and a plurality of peripheral units each of which is provided with a coupling unit for controlling the local operation thereof, generating a signal on an output thereof each time the controlled peripheral unit is ready for an exchange and routing information to and from the said peripheral unit during an exchange operation, wherein such exchange operations are made through and controlled from a microprogrammed processor having external store word and address accesses and coupling unit addressable accesses from a read-write register of a zone organized microprogram processing store and arithmetical unit thereof, said microprogram processing store including a zone address register and said microprogrammed processor further comprising a zone organized microprogram store including interpretative peripheral coupling function micro-instructions in addressed zones thereof, a zone address register and a read-write register in said microprogram store, and wherein the microprogrammed processor comprises as many exchange microprogram zone address code forming circuits and as many exchange microprogram processing zone address code forming circuits as are coupling units, each such address code forming circuit being activable from the ready-for-exchange signal from a coupling unit, a logical OR circuit of the readyfor-exchange signals from the coupling units, first and second gate circuits activable from the output of the said logical OR circuit having respective outputs connected to forcing inputs of the zone address registers of the microprogram store and of the microprogram processing store, said first gate circuit having an input connected to the outputs of the exchange microprogram zone address code forming circuits and said second gate circuit having an input connected to the outputs of the exchange microprogram processing zone address code forming circuits.
Claim 2
Dependent Claim
289 words
A digital data processing system for exchange operations between an external instruction and operand word external store and a plurality of peripheral units each of which is provided with a coupling unit for controlling the local operation thereof, generating a signal on an output thereof each time the controlled peripheral unit is ready for an exchange and routing information to and from the said peripheral unit during an exchange operation, wherein such exchange operations are made through and controlled from a microprogrammed processor having external store word and address accesses and coupling unit addressable accesses from a read-write register of a zone organized microprogram processing store and arithmetical unit thereof, said microprogram processing store including a zone address register and said microprogrammed processor further comprising a zone organized microprogram store including interpretative peripheral coupling function micro-instructions in addressed zones thereof, a zone address register and a read-write register in said microprogram store, and wherein the microprogrammed processor comprises as many exchange microprogram zone address code forming circuits and as many exchange microprogram processing zone address code forming circuits as are coupling units, each such address code forming circuit being activable from the ready-for-exchange signal from a coupling unit, a logical OR circuit of the readyfor-exchange signals from the coupling units, first and second gate circuits activable from the output of the said logical OR circuit having respective outputs connected to forcing inputs of the zone address registers of the microprogram store and of the microprogram processing store, said first gate circuit having an input connected to the outputs of the exchange microprogram zone address code forming circuits and said second gate circuit having an input connected to the outputs of the exchange microprogram processing zone address code forming circuits.
Claim 3
Dependent Claim
45 words
System according to claim 1, wherein a micro-instruction acquitment signal being conventionally generated in the microprogrammed processor at each termination of execution of a micro-instruction, said first and second gate circuits are provided with an activation input to which such an acquitment signal is applied.
Claim 4
Dependent Claim
69 words
System according to claim 1, wherein the ready-for-exchange signals from the coupling units are applied to a peripheral hierarchized priority defining circuit, the outputs of which are applied to the inputs of the said logical OR circuit and gaTes individually controlled from the outputs of the said peripheral hierarchized priority defining circuits are applied to as many gates in the activation inputs of the said address code forming circuits.
Claim 5
Dependent Claim
56 words
System according to claim 2, wherein a gate circuit receives the output signal from said logical OR circuit and the said acquitment signal and has its output connected to means transferring the context of an interrupted task of the microprogrammed processor to memorization locations thereof prior to activation of the said first and second gate circuits.
Claim 6
Dependent Claim
62 words
Digital data processor according to claim 1, wherein said microprogrammed machine comprises a first word buffer register and a second word buffer register respectively interposed between the instruction and operand word access to the external store and the micro-programme store and between the external store address access to the external store and the processing store of the micro-programmed machine of the processor.
Claim 7
Dependent Claim
153 words
A digital data processing system for exchange operations between an instruction word and operand store and a plurality of peripheral units each of which is associated with coupling units, through a processor organized as a microprogrammed machine having microprogram zone organized store including a zone address register, microprogram processing zone organized store including a zone address register and a read-write register association with an arithmetical unit, each coupling unit delivering a ready-for-exchange condition signal when its peripheral unit is in such a condition, wherein said microprogrammed machine processor comprises word buffer access and address buffer access to the store and addressable accesses to the coupling units from the read-write register and an exchange control organization activated from the ready-for-exchange signals from the coupling units, forming exchange microprogram and microprogram processing zone address codes and forcing said codes into the corresponding zone address registers and of the microprogram store and the microprogram processing store.
Claim 8
Dependent Claim
153 words
A digital data processing system for exchange operations between an instruction word and operand store and a plurality of peripheral units each of which is associated with coupling units, through a processor organized as a microprogrammed machine having microprogram zone organized store including a zone address register, microprogram processing zone organized store including a zone address register and a read-write register association with an arithmetical unit, each coupling unit delivering a ready-for-exchange condition signal when its peripheral unit is in such a condition, wherein said microprogrammed machine processor comprises word buffer access and address buffer access to the store and addressable accesses to the coupling units from the read-write register and an exchange control organization activated from the ready-for-exchange signals from the coupling units, forming exchange microprogram and microprogram processing zone address codes and forcing said codes into the corresponding zone address registers and of the microprogram store and the microprogram processing store.
Claim 9
Dependent Claim
71 words
A digital data processing system comprising the combination of a central instruction and operand store and a plurality of multiple peripheral coupled processor units each of which is organized as a microprogrammed machine for execution of the instructions from said central store and each of which further comprises means executing the coupling functions useful for establishing exchange operations between said peripheral units and said central store by the said micro-programmed machine.
Claim 10
Dependent Claim
71 words
A digital data processing system comprising the combination of a central instruction and operand store and a plurality of multiple peripheral coupled processor units each of which is organized as a microprogrammed machine for execution of the instructions from said central store and each of which further comprises means executing the coupling functions useful for establishing exchange operations between said peripheral units and said central store by the said micro-programmed machine.
References Cited (Backward Citations)
US3651482A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-22 | 1977-04-23 | 1977-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-22 | 1981-04-23 | 1981-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-22 | 1985-04-23 | 1985-10-23 | $7700.00 | Window Closed / Lapsed |