Patent US4075687A successfully refreshed from Google Patents.
US4075687A
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Microprogram controlled digital computer
Assignee: Raytheon Co
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Filing: 1976-03-01
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Granted: 1978-02-21
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Expires: 1996-03-01
Abstract
Abstract A microinstruction memory addressing control unit for a microprogram controlled digital computer is disclosed. The microinstruction memory stores an addressable fetch microprogram and independent sets of addressable microinstructions. Each one of the stored microinstructions in the sets thereof has an addressing control field. The microinstruction memory addressing control unit, in response to the microinstruction control field of a microinstruction currently under execution, is adapted to select as the next address for the memory one of a variety of addresses.
Inventors
- 👤 Stanley M. Nissen
- 👤 Steven J. Wallach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/265
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
207 words
A digital computer wherein a microinstruction memory stores an addressable fetch microprogram and independent sets of addressable microinstructions, each set of microinstructions including a last microinstruction for calling the fetch microprogram, and each one of the stored microinstructions in the sets thereof has an addressing control field, a microinstruction memory addressing control unit, comprising: a. a first storage means for storing the beginning address of the fetch microprogram; b. second storage means, responsive to a microinstruction in a first set of microinstructions under execution, for storing the address of a different microinstruction in such first set of microinstructions; c. means for producing a control signal in accordance with a first portion of the addressing control field of one of the microinstructions in the first set of microinstructions; and d . selector means, responsive to the control signal and a second portion of the addressing control field of the last microinstruction in a second one of the sets of microinstructions under execution, for coupling to the microinstruction memory as the next address for such memory either the beginning address of the fetch microprogram stored in the first storage means or the address of the different microinstruction in the first set of microinstructions stored in the second storage means.
Claim 2
Dependent Claim
207 words
A digital computer wherein a microinstruction memory stores an addressable fetch microprogram and independent sets of addressable microinstructions, each set of microinstructions including a last microinstruction for calling the fetch microprogram, and each one of the stored microinstructions in the sets thereof has an addressing control field, a microinstruction memory addressing control unit, comprising: a. a first storage means for storing the beginning address of the fetch microprogram; b. second storage means, responsive to a microinstruction in a first set of microinstructions under execution, for storing the address of a different microinstruction in such first set of microinstructions; c. means for producing a control signal in accordance with a first portion of the addressing control field of one of the microinstructions in the first set of microinstructions; and d . selector means, responsive to the control signal and a second portion of the addressing control field of the last microinstruction in a second one of the sets of microinstructions under execution, for coupling to the microinstruction memory as the next address for such memory either the beginning address of the fetch microprogram stored in the first storage means or the address of the different microinstruction in the first set of microinstructions stored in the second storage means.
Claim 3
Dependent Claim
125 words
The computer recited in claim 1 wherein the selector means includes an output selector comprising: a first input coupled to a third portion of the addressing control field of one of the microinstructions in the second set of microinstructions under execution; a second input terminal coupled to either the first or second storage means selectively in accordance with the control signal; and an output terminal coupled to the microinstruction memory, such output selector coupling to such output terminal either the first input terminal or the second input terminal selectively in accordance with the second portion of the addressing control field of the microinstruction in the second set of microinstructions under execution, such output terminal feeding to such microinstruction memory the next address for such memory.
Claim 4
Dependent Claim
175 words
A digital computer wherein a microinstruction memory stores sets of addressable microinstructions and wherein each one of such stored microinstructions has a microinstruction memory addressing control field, a microinstruction memory addressing control unit comprising: a. means for producing a plurality of condition signals; b. condition selector means, responsive to a first portion of the addressing control field of one of the microinstructions in a first set of microinstructions under execution, for selecting one of the plurality of condition signals; c. storage means for storing, in response to one of the microinstructions in a second set of microinstructions under execution, the address of the microinstruction under execution displaced by a predetermined number; and d. selector means, responsive to the selected condition signal produced in response to execution of the microinstruction in the first set thereof, for coupling to the microinstruction memory as the next address for such memory either the address stored in the storage means or a second portion of the addressing control field of the microinstruction in the first set of microinstructions under execution.
Claim 5
Dependent Claim
175 words
A digital computer wherein a microinstruction memory stores sets of addressable microinstructions and wherein each one of such stored microinstructions has a microinstruction memory addressing control field, a microinstruction memory addressing control unit comprising: a. means for producing a plurality of condition signals; b. condition selector means, responsive to a first portion of the addressing control field of one of the microinstructions in a first set of microinstructions under execution, for selecting one of the plurality of condition signals; c. storage means for storing, in response to one of the microinstructions in a second set of microinstructions under execution, the address of the microinstruction under execution displaced by a predetermined number; and d. selector means, responsive to the selected condition signal produced in response to execution of the microinstruction in the first set thereof, for coupling to the microinstruction memory as the next address for such memory either the address stored in the storage means or a second portion of the addressing control field of the microinstruction in the first set of microinstructions under execution.
Claim 6
Dependent Claim
146 words
A digital computer wherein a microinstruction memory stores sets of addressable microinstructions and wherein each one of such stored microinstructions has a microinstruction memory addressing control field, and a microinstruction memory addressing control unit comprising: a. means for producing a plurality of condition signals; b. condition selector means, responsive to a first portion of the addressing control field of a microinstruction under execution, for selecting one of the plurality of condition signals; c. displacing means, coupled to a second portion of the addressing control field of the same microinstruction under execution, for displacing such second portion a predetermined number; d. selector means, responsive to the selected condition signal, for coupling to the microinstruction memory as the next address for such memory either the second portion of the addressing control field of the same microinstruction under execution or the displaced second portion of the addressing control field.
Claim 7
Dependent Claim
146 words
A digital computer wherein a microinstruction memory stores sets of addressable microinstructions and wherein each one of such stored microinstructions has a microinstruction memory addressing control field, and a microinstruction memory addressing control unit comprising: a. means for producing a plurality of condition signals; b. condition selector means, responsive to a first portion of the addressing control field of a microinstruction under execution, for selecting one of the plurality of condition signals; c. displacing means, coupled to a second portion of the addressing control field of the same microinstruction under execution, for displacing such second portion a predetermined number; d. selector means, responsive to the selected condition signal, for coupling to the microinstruction memory as the next address for such memory either the second portion of the addressing control field of the same microinstruction under execution or the displaced second portion of the addressing control field.
Claim 8
Dependent Claim
200 words
A digital computer wherein a microinstruction memory stores addressable microinstructions and wherein each one of such stored microinstructions has a microinstruction memory addressing control field and a microinstruction memory addressing control unit comprising: a. means for producing a plurality of condition signals; b. condition selector means, responsive to a first portion of the addressing control field of a first microinstruction under execution, for selecting one of the plurality of condition signals; c. storage means for storing, in response to a second microinstruction under execution, the address of the second microinstruction under execution displaced by a predetermined number; d. first selector means, responsive to a second portion of the addressing control field of the first microinstruction under execution, for coupling to the output terminal of such first selector means either the storage means or a third portion of the addressing control field of the first microinstruction under execution displaced by a predetermined number; and e. output selector means, responsive to the selected condition signal, for coupling to the microinstruction memory as the next address for such memory either the output terminal of the first selector means or the second portion of the addressing control field of the first microinstruction under execution.
Claim 9
Dependent Claim
200 words
A digital computer wherein a microinstruction memory stores addressable microinstructions and wherein each one of such stored microinstructions has a microinstruction memory addressing control field and a microinstruction memory addressing control unit comprising: a. means for producing a plurality of condition signals; b. condition selector means, responsive to a first portion of the addressing control field of a first microinstruction under execution, for selecting one of the plurality of condition signals; c. storage means for storing, in response to a second microinstruction under execution, the address of the second microinstruction under execution displaced by a predetermined number; d. first selector means, responsive to a second portion of the addressing control field of the first microinstruction under execution, for coupling to the output terminal of such first selector means either the storage means or a third portion of the addressing control field of the first microinstruction under execution displaced by a predetermined number; and e. output selector means, responsive to the selected condition signal, for coupling to the microinstruction memory as the next address for such memory either the output terminal of the first selector means or the second portion of the addressing control field of the first microinstruction under execution.
Claim 10
Dependent Claim
45 words
The computer recited in claim 5 including an additional storage means coupled to a third input terminal of the first selector means, for storing, in response to a third microinstruction under execution, the address of such third microinstruction under execution displaced by a predetermined number.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-20 | 1981-08-22 | 1982-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-20 | 1985-08-22 | 1986-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-20 | 1989-08-22 | 1990-02-21 | $7700.00 | Window Closed / Lapsed |