US3930236A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Small micro program data processing system employing multi-syllable micro instructions
Assignee: Unisys Corp
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Filing: 1973-10-02
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Granted: 1975-12-30
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Expires: 1993-10-02
Abstract
Abstract A micro program system is disclosed which employs two levels of subinstruction sets. The first level of subinstructions, or micro instructions, is implemented by a second level of control instructions that can be stored in a processor read-only memory. The respective micro instructions are made up of varying numbers of syllables according to the function of the particular micro instructions. The various types of micro instruction syllables are stored in a micro instruction memory to be fetched therefrom in sequence in accordance with the requirements of a particular micro instruction or subject instruction. In this manner, a variety of micro instructions can be created by selecting a plurality of different syllables from the micro instruction memory. A different micro instruction syllable is provided to specify each combination of the function to be performed and the source and destination registers to be used with the particular buses in the processor.
Inventors
- 👤 Alisdair Cullen Ferguson
- 👤 John Mcgregor
- 👤 Alastair George Macpherson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223; G06F9/226; G06F9/26
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
206 words
A data processing system including a processor having a fixed data path width and a memory having a first portion to store macro instructions and data and a second portion to store different types of micro instruction syllables, each syllable having a width equal to said fixed data path width, said processor comprising: a function unit to perform logical operations on data; a plurality of registers coupled to said function unit for data transfer therebetween; macro instruction accessing means coupled to said memory to receive macro instruction operators from said first memory portion; and micro instruction accessing means coupled to said function unit and said registers, said micro instruction accessing means also being coupled to said macro instruction accessing means and to said second memory portion and responsive to said macro instruction operator to access, in sequence, two or more micro instruction syllables from said second portion of said memory so as to form a micro instruction called for by said macro instruction operator wherein the first syllable of said micro instruction specifies a logical operation to be performed by said function unit and the particular ones of said plurality of registers for data transfer to said function unit and the remaining syllables specify literal values.
Claim 2
Dependent Claim
206 words
A data processing system including a processor having a fixed data path width and a memory having a first portion to store macro instructions and data and a second portion to store different types of micro instruction syllables, each syllable having a width equal to said fixed data path width, said processor comprising: a function unit to perform logical operations on data; a plurality of registers coupled to said function unit for data transfer therebetween; macro instruction accessing means coupled to said memory to receive macro instruction operators from said first memory portion; and micro instruction accessing means coupled to said function unit and said registers, said micro instruction accessing means also being coupled to said macro instruction accessing means and to said second memory portion and responsive to said macro instruction operator to access, in sequence, two or more micro instruction syllables from said second portion of said memory so as to form a micro instruction called for by said macro instruction operator wherein the first syllable of said micro instruction specifies a logical operation to be performed by said function unit and the particular ones of said plurality of registers for data transfer to said function unit and the remaining syllables specify literal values.
Claim 3
Dependent Claim
17 words
A system according to claim 1 wherein: the second portion of said memory is a read-only memory.
Claim 4
Dependent Claim
273 words
A data processing system including a processor having a fixed data path width and a memory having a first portion to store macro instructions and data and a second portion to store different types of micro instruction syllables, each syllable having a width equal to said fixed data path width, said processor comprising: a function unit to perform logical operations on data; a plurality of registers coupled to said function unit for data transfer therebetween; macro instruction accessing means coupled to said memory to receive macro instruction operators from said first memory portion; micro instruction accessing means coupled to said macro instruction accessing means and to said second memory portion and responsive to said macro instruction operator to access, in sequence, two or more micro instruction syllables from said second portion of said memory so as to form a micro instruction called for by said macro instruction operator wherein the first syllable of said micro instruction specifies a logical operation to be performed by said function unit and the particular ones of said plurality of registers for data transfer to said function unit and the remaining syllables specify literal values; and a control memory coupled to said function unit and said registers and also to said micro instruction Accessing means, said control memory containing control instructions individually selectable from said control memory in response to the first micro instruction syllable of a micro instruction to initiate data transfer between individual ones of said registers and said function unit such that there is a unique micro instruction syllable to specify each combination of registers to be employed and the logical operation to be performed.
Claim 5
Dependent Claim
273 words
A data processing system including a processor having a fixed data path width and a memory having a first portion to store macro instructions and data and a second portion to store different types of micro instruction syllables, each syllable having a width equal to said fixed data path width, said processor comprising: a function unit to perform logical operations on data; a plurality of registers coupled to said function unit for data transfer therebetween; macro instruction accessing means coupled to said memory to receive macro instruction operators from said first memory portion; micro instruction accessing means coupled to said macro instruction accessing means and to said second memory portion and responsive to said macro instruction operator to access, in sequence, two or more micro instruction syllables from said second portion of said memory so as to form a micro instruction called for by said macro instruction operator wherein the first syllable of said micro instruction specifies a logical operation to be performed by said function unit and the particular ones of said plurality of registers for data transfer to said function unit and the remaining syllables specify literal values; and a control memory coupled to said function unit and said registers and also to said micro instruction Accessing means, said control memory containing control instructions individually selectable from said control memory in response to the first micro instruction syllable of a micro instruction to initiate data transfer between individual ones of said registers and said function unit such that there is a unique micro instruction syllable to specify each combination of registers to be employed and the logical operation to be performed.
Claim 6
Dependent Claim
213 words
A data processing system including a processor having a fixed data path width and a memory to store different types of micro instruction syllables, each having a width equal to said fixed data path width, said processor comprising: a function unit to perform logical operations on data; a plurality of registers coupled to said function unit for data transfer therebetween; micro instruction accessing means coupled to said memory to access in sequence two or more micro instruction syllables from said memory so as to form a micro instruction wherein the first syllable of said micro instruction specifies a logical operation to be performed by said function unit and the particular ones of said plurality of registers for data transfer to said function unit and the remaining syllables specify literal values; and a control memory coupled to said function unit and said registers and also to said micro instruction accessing means, said control memory containing control instructions individually selectable from said control memory in response to the first micro instruction syllable of a micro instruction to initiate data transfer between individual ones of said registers and said function unit such that there is a unique micro instruction syllable to specify each combination of registers to be employed and the logical operation to be performed.
Claim 7
Dependent Claim
213 words
A data processing system including a processor having a fixed data path width and a memory to store different types of micro instruction syllables, each having a width equal to said fixed data path width, said processor comprising: a function unit to perform logical operations on data; a plurality of registers coupled to said function unit for data transfer therebetween; micro instruction accessing means coupled to said memory to access in sequence two or more micro instruction syllables from said memory so as to form a micro instruction wherein the first syllable of said micro instruction specifies a logical operation to be performed by said function unit and the particular ones of said plurality of registers for data transfer to said function unit and the remaining syllables specify literal values; and a control memory coupled to said function unit and said registers and also to said micro instruction accessing means, said control memory containing control instructions individually selectable from said control memory in response to the first micro instruction syllable of a micro instruction to initiate data transfer between individual ones of said registers and said function unit such that there is a unique micro instruction syllable to specify each combination of registers to be employed and the logical operation to be performed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-29 | 1979-06-30 | 1979-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-29 | 1983-06-30 | 1983-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-29 | 1987-06-30 | 1987-12-30 | $7700.00 | Window Closed / Lapsed |