Computer

Claim 2

A computer for performing a plurality of arithmetic operations including combinations of addition and multiplication in response to a single instruction, said computer comprising a data processing unit for performing multiplication, a plurality of individual data storage means, means for supplying individual data words to each of said data storage means, means for connecting said data storage means to said processing unit, means for accumulating the product output from said processing unit, and means responsive to a single command for causing a plurality of sequential transfers of data words from groups of said data storage means to said processing unit for processing and from said processing unit to said accumulator.

Claim 3

The computer defined in claim 1 wherein said command responsive means comprises a control unit which receives an instruction and generates the signals required to cause said processing unit to process information supplied thereto.

Claim 4

A computer comprising a plurality of registers for temporarily storing information, a processing unit for performing multiplication, means for connecting said registers individually to said processing unit for the transfer of information therebetween, a control unit for translating individual instructions into signals for causing a plurality of transfers of information from groups of registers in sequence to said processing unit and the processing of information presented to said processing unit at any time, an accumulator connected to accumulate the outputs from said processing unit during an individual instruction, and means for supplying single instructions to said control unit.

Claim 5

A computer comprising a plurality of registers for temporarily storing information, a processing unit for performing multiplication, means for connecting said registers individually to said processing unit for the transfer of information therebetween, a control unit for translating individual instructions into signals for causing a plurality of transfers of information from groups of registers in sequence to said processing unit and the processing of information presented to said processing unit at any time, an accumulator connected to accumulate the outputs from said processing unit during an individual instruction, and means for supplying single instructions to said control unit.

Claim 6

The computer defined in claim 3 wherein said registers are each a one-word register, and wherein information is transferred from two of said registers at one time to said processing unit for processing.

Claim 7

The computer defined in claim 3 wherein said plurality of registers comprise two banks of registers and wherein the information applied to one bank of registers comprises a first series and the information applied to the second bank of registers comprises a second series, and wherein said processing unit processes the information from each pair of registers in sequence.

Claim 8

A computer comprising apparatus for performing a plurality of arithmetiC operations in response to a single instruction, said apparatus comprising a plurality of registers arranged in pairs, means for applying to each of said registers a data word, a data processor having at least two inputs and an output capable of multiplying two data words and producing the product thereof, means for connecting the outputs of each of the registers to an input of said processor so that pairs of data words appear at the inputs to the processor at the same time, an accumulator connected to the output of said processor to accumulate the products produced thereby, a control unit responsive to individual instructions to cause pairs of data words to be transferred to the inputs of said processor in sequence so that one is multiplied by another and to cause the results of said multiplication to be transferred to said accumulator, and means for applying individual instructions to said control unit.

Claim 9

A computer comprising apparatus for performing a plurality of arithmetiC operations in response to a single instruction, said apparatus comprising a plurality of registers arranged in pairs, means for applying to each of said registers a data word, a data processor having at least two inputs and an output capable of multiplying two data words and producing the product thereof, means for connecting the outputs of each of the registers to an input of said processor so that pairs of data words appear at the inputs to the processor at the same time, an accumulator connected to the output of said processor to accumulate the products produced thereby, a control unit responsive to individual instructions to cause pairs of data words to be transferred to the inputs of said processor in sequence so that one is multiplied by another and to cause the results of said multiplication to be transferred to said accumulator, and means for applying individual instructions to said control unit.