US3900835A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Branching circuit for microprogram controlled central processor unit
Assignee: Digital Equipment Corp
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Filing: 1973-09-24
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Granted: 1975-08-19
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Expires: 1993-09-24
Abstract
Abstract A central processor unit under the control of microprogram words retrieved from a storage facility in sequence. A control section in each microprogram word contains information used to define data paths while an address portion identifies the location of the next microprogram word in sequence. A buffer register receives each microprogram word, the address passing through a modification circuit. If a first microprogram word sets up branching conditions within the central processor unit, other circuitry establishes an address offset which is applied to a base address contained in the next microprogram word to thereby alter the location of the following microprogram word. Thus, any microprogram word which can produce a branch must be followed with an other microprogram word which does not depend upon the branch conditions, but which contains a base address.
Inventors
- 👤 C Gordon Bell
- 👤 John E Buzynski
- 👤 Charles H Kaman
- 👤 James F O'loughlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/261; G06F9/262; G06F9/264
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
A microprogram configured central processor comprising: A. a read-only memory for storing microprogram words, each microprogram word having a control portion and an address portion for at least partly identifying the next word to be retrieved in sequence, at least one of the microprogram words being a branching word, B. a modifier circuit receiving the address portion of each microprogram word retrieved from memory and for modifying that address in response to certain conditions, C. a buffer register for storing each microprogram word to be executed in sequence, said buffer register being connected for receiving directly the control portion of a microprogram word from said memory, said read-only memory including means for retrieving a next word thereupon in response to the address portion in said buffer register. D. timing means for defining alternate ready and transfer intervals, said modifier circuit being enabled during a ready interval and producing a modified address for transfer to said buffer register during a subsequent transfer interval.
Claim 2
Dependent Claim
162 words
A microprogram configured central processor comprising: A. a read-only memory for storing microprogram words, each microprogram word having a control portion and an address portion for at least partly identifying the next word to be retrieved in sequence, at least one of the microprogram words being a branching word, B. a modifier circuit receiving the address portion of each microprogram word retrieved from memory and for modifying that address in response to certain conditions, C. a buffer register for storing each microprogram word to be executed in sequence, said buffer register being connected for receiving directly the control portion of a microprogram word from said memory, said read-only memory including means for retrieving a next word thereupon in response to the address portion in said buffer register. D. timing means for defining alternate ready and transfer intervals, said modifier circuit being enabled during a ready interval and producing a modified address for transfer to said buffer register during a subsequent transfer interval.
Claim 3
Dependent Claim
34 words
A microprogram configured central processor as recited in claim 1, wherein said modifier circuit comprises a microbranch encoding means for receiving a plurality of control signals and generating an address modifier in response thereto.
Claim 4
Dependent Claim
39 words
A microprogram configured central processor as recited in claim 2 wherein said modifier circuit additionally includes means for generating a plurality of condition signals representing internal processor conditions, said microbranch encoding means being additionally responsive to the condition signals.
Claim 5
Dependent Claim
90 words
A microprogram configured central processor as recited in claim 3 wherein said microbranch encoding means is adapted for generating a plurality of sets of address modifications signals, said modifier circuit additionally comprising a microbranch multiplexer for selectively coupling one set of modifying signals therethrough, the selection being dependent upon the contents of a branching field in the control portion of the microprogram word contained in said buffer register, and means for combining the address from said read-only memory and said selected set of modifying signals for generating the modified address.
Claim 6
Dependent Claim
122 words
A read-only memory for use in a microprogram controlled digital computer including means for generating address signals to obtain words from said memory in sequence, said memory including a plurality of locations for storing microprogram words, each microprogram word comprising a control portion and an address portion, certain of said locations storing branch microprogram words for establishing branches, each Branch microprogram word including in the address portion, an address of a next location in the memory, the contents of the next location being a microprogram word with a base address in the address portion thereof for modification in accordance with the control portion of the branch microprogram word, the modified address being the the location of a first microprogram in the branch.
Claim 7
Dependent Claim
122 words
A read-only memory for use in a microprogram controlled digital computer including means for generating address signals to obtain words from said memory in sequence, said memory including a plurality of locations for storing microprogram words, each microprogram word comprising a control portion and an address portion, certain of said locations storing branch microprogram words for establishing branches, each Branch microprogram word including in the address portion, an address of a next location in the memory, the contents of the next location being a microprogram word with a base address in the address portion thereof for modification in accordance with the control portion of the branch microprogram word, the modified address being the the location of a first microprogram in the branch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-18 | 1979-02-17 | 1979-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-18 | 1983-02-17 | 1983-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-18 | 1987-02-17 | 1987-08-19 | $7700.00 | Window Closed / Lapsed |