Data processing control system

Claim 2

A data processing system comprising: data register means for containing data to be processed; register control logic means for operating on data contained within said data register means; an addressable memory unit including: an instruction section having a plurality of outputs for causing different operations to occur in said data registers; a qualifier section having a plurality of condition outputs defining predetermined testable data conditions within said data register means, said qualifier section also having an inhibit signal output representing that instructions are not to be read out from said instruction section; means for gating the outputs from said instruction section to said register control logic means, said gating means having a gate control input; register condition logic for providing outputs indicating conditions existing within said data register means; comparison means for comparing the outputs from said qualifier section and said register condition logic and for generating a qualifier signal indicating when a predetermined relationship exists between said last named outputs; and control logic means having an output coupled to the gate control input of said gating means for operating said gating means to inhibit the readout of instructions from said instruction section to said register control logic in response to concurrence of the qualifier signal from said comparison means and the inhibit signal from said qualifier section.

Claim 3

The system of claim 1, said memory unit further including: an address portion for providing address signals, said address portion including means for selectively gating signals therefrom.

Claim 4

The system of claim 2, said address portion including a direct address section and an alternate address section, said direct and alternate address sections being separately selectable by the gating means of said address portion.

Claim 5

The system of claim 3, said control logic means being operable in an iterative control loop having first and second steps of operation, said control logic means including: means operable during said first step for enabling said qualifier section and for cycling said memory unit to read out of said memory unit the addressed qualifier signals; means operable during said second step and simultaneously with said means for gating the output signals from said instruction section to said register control logic means for enabling the gating means of either the direct or alternate address sections of said address portion and for cycling said memory unit to select the next location in said memory unit which is addressed by said address portion.

Claim 6

A data processing system comprising: a cyclically operable addressable memory unit including: an instruction section for producing data processing instruction signals; a qualifier section for producing qualifier signals representative of predetermined data conditions, and first and second inhibit signals for indicating that said instruction signals are to be inhibited if said predeterMined data conditions are met and not met, respectively; an address portion for providing address signals to direct selection of data bits from said memory unit; each of said instruction section, said qualifier section and said address portion including gating means for selecting signals therefrom; a plurality of registers for containing data to be processed; logic means for operating on the data in said registers in response to said instruction signals; means for indicating predetermined conditions of the contents of selected ones of said registers; comparing means responsive to selected qualifier signals and said indicating means for providing an output signal having first and second states for indicating that the predetermined data conditions represented by said selected qualifier signals are met and not met, respectively; and control logic means for selectively enabling the gating means of said instruction section, said qualifier section and said address portion and for cycling said memory unit, said control logic means including means for inhibiting the readout of instruction signals in response to the concurrence of said first inhibit signal and said first state of said output signal, and in response to the concurrence of said second inhibit signal and said second state of said output signal during a time interval when said last named instruction signals are addressed by the same address as said selected qualifier signals applied to said comparing means.

Claim 7

A data processing system comprising: a cyclically operable addressable memory unit including: an instruction section for producing data processing instruction signals; a qualifier section for producing qualifier signals representative of predetermined data conditions, and first and second inhibit signals for indicating that said instruction signals are to be inhibited if said predeterMined data conditions are met and not met, respectively; an address portion for providing address signals to direct selection of data bits from said memory unit; each of said instruction section, said qualifier section and said address portion including gating means for selecting signals therefrom; a plurality of registers for containing data to be processed; logic means for operating on the data in said registers in response to said instruction signals; means for indicating predetermined conditions of the contents of selected ones of said registers; comparing means responsive to selected qualifier signals and said indicating means for providing an output signal having first and second states for indicating that the predetermined data conditions represented by said selected qualifier signals are met and not met, respectively; and control logic means for selectively enabling the gating means of said instruction section, said qualifier section and said address portion and for cycling said memory unit, said control logic means including means for inhibiting the readout of instruction signals in response to the concurrence of said first inhibit signal and said first state of said output signal, and in response to the concurrence of said second inhibit signal and said second state of said output signal during a time interval when said last named instruction signals are addressed by the same address as said selected qualifier signals applied to said comparing means.

Claim 8

The system of claim 2, said memory unit further including means responsive to an address signal from said address portion for simultaneously addressing predetermined memory locations in said instruction section, said qualifier section and said address portion.

Claim 9

The system of claim 5, further including means responsive to a single address signal from said address portion for simultaneously addressing predetermined memory locations in said instruction section, said qualifier section and said address portion.