Regenerator circuit for CCD elements

Claim 2

Regenerator circuit for CCD elements comprising a first CCD and a second CCD, a first MOS capacitance, a second capacitance connected in series with said first capacitance, the point at which said two capacitances are connected in series with one another being the output of said regenerator circuit and being connected to an input electrode of said second CCD, the output of said first CCD including an output stage, an output diffusion zone, a terminal to which a potential φ v can be connected, a transistor connected on the one hand to said point and on the other hand to said terminal, a gate electrode of said transistor being connected by a line to said output diffusion zone of said first CCD stage.

Claim 3

Process for operating a circuit as set forth in claim 1 in which the output capacitance of said output stage is pre-charged to a reference potential U ref (time t 1 and t 2 ), said output capacitance being formed by the overall capacitance of said diffusion zone, the gate capacitance of said transistor and the capacitance of said connection line between said transistor and said output diffusion zone, and that in order that the output capacitance of said first CCD be charged to the reference potential U ref the latter is connected to a second diffusion zone of said first CCD, which, together with the first output diffusion zone and a gate electrode forms a field effect transistor, which field effect transistor is switched conductive as a result of the connection of a potential φ R to its gate electrode, that from the first CCD a quantity of charge corresponding to a binary 1 or a binary 0 is pulsed to said first output diffusion zone (time t 3 ), that the quantity of charge corresponding to a binary 1 results in a change in voltage U A ' across said first capacitance, and that a quantity of charge corresponding to a binary 0 results in no change in voltage across said first capacitance, that said transistor is switched conductive by the potential φ v across its terminal (time t 4 ), as a result of which in the case of a binary 1 the second capacitance is pre-charged to the potential U ref - ΔU A ' - U T4 and in the case of a binary 0 is pre-charged to the potential U ref - U T4 , that a pulse train φ B to said electrode of said MOS capacitor is switched on (time t 5 ) as a result of which due to capacitive coupling the voltage across said second capacitance is raised to a maximum limit U Emax ' in the case of a binary 1, and to the maximum limit U Emax ' + k .sup.. ΔU E in the case of a binary 0, and that in the case of a binary 0, the voltage U ref - U T4 is greater than the start voltage of the MOS capacitor.

Claim 4

Regenerator circuit for CCD elements comprising a first MOS capacitance, a second capacitance connected in series with said first capacitance, the point at which said two capacitances are connected in series with one another being the output of the regenerator circuit and being connected to an input electrode of an input CCD, a terminal to which a potential φ v can be connected, a transistor connected on the one hand to said point and on the other hand to said terminal, a gate electrode of said transistor being connected via a line to an output diffusion zone of an output CCD stage.

Claim 5

Regenerator circuit for CCD elements comprising a first MOS capacitance, a second capacitance connected in series with said first capacitance, the point at which said two capacitances are connected in series with one another being the output of the regenerator circuit and being connected to an input electrode of an input CCD, a terminal to which a potential φ v can be connected, a transistor connected on the one hand to said point and on the other hand to said terminal, a gate electrode of said transistor being connected via a line to an output diffusion zone of an output CCD stage.

Claim 6

Regenerator circuit as set forth in claim 3, in which said first capacitance consists of the input capacitance of the connected CCD circuit.

Claim 7

Regenerator circuit as set forth in claim 3 which is constructed in a MOS-aluminum-silion-gate field effect technique.

Claim 8

Regenerator circuit as set forth in claim 3 which is constructed in a solid-silicon-technique or in a SOS technique.