US3760381A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stored charge memory detection circuit
Assignee: International Business Machines Corp
•
Filing: 1972-06-30
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Granted: 1973-09-18
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Expires: 1992-06-30
Abstract
Abstract A sensing circuit which is responsive to binary information represented by the level of charge in a capacitor is disclosed. The circuit comprises a differential amplifier; the nodes of which are connected to bucket brigade sense amplifier arrangements which are in turn connected to bit lines to which a plurality of memory device which store information in the form of charge are connected. Each bit line portion connected to the bucket brigade sense amplifier represents half of a bit line to which a plurality of storage devices (such as a capacitor in series with an FET gate) are connected. Each half of the bit line is also connected to a reference capacitor via an actuable FET device or other stored charge memory device. Each of the bucket brigade sense amplifiers consists of an output capacitance which is connected in parallel with the bit line capacitances of each half of the bit line via an actuable FET device. A source of voltage for charging the bit line capacitances is connected to the bit line halves via an actuable FET device and is utilized to charge the bit line capacitance, the output capacitance and a reference capacitor of one of the bit line halves. In operation, both bit line halves are charged to some voltage which is usually equal to the voltage to which the capacitance of a selected memory cell can be charged. At the same time, a reference capacitor is charged to approximately one half the voltage to which the selected cell capacitance can be charged. If the reference capacitor is to be charged to half the voltage of a storage cell, the size of the reference capacitor should be equal to that of the storage capacitor. Another way of implementing the reference capacitor is to use a reference capacitor half the size of a storage capacitor and discharge it completely each time before selecting a memory cell. If the memory cell capacitor is charged to full voltage (representing a binary ''''1'''') when the word line of the memory cell is activated for reading, no charge will flow from the bit line capacitance to the memory cell capacitance because both are at the same level. If the memory cell capacitance were empty (representing a binary ''''0'''') charge would flow from the bit line capacitance when reading occurred, filling the memory capacitor and reducing the bit line capacitor voltage by a small ion. When the bucket brigade circuit is actuated, no charge transfer occurs where the memory capacitor was full and a voltage approximately equal to the bit line charging voltage appears on one node of the differential amplifier. Where the memory capacitor was initially empty, charge transfer occurs to refill the bit line capacitance to its original level thereby depleting the output capacitance of charge and causing zero potential to be applied to one node of the differential amplifier. Simultaneously, with the appearance of the bit line charging voltage or zero at one node of the differential amplifier, a voltage equal to approximately half the bit line charging voltage appears at the other node of the differential amplifier. This results from the charging of the reference capacitance to one half the charging voltage. When reading of the reference capacitance occurs, charge from the bit line capacitance charges the reference capacitor up to its full value, depleting the bit line capacItance of an amount of charge equal to half the charge depleted from the opposite bit line capacitance when a memory cell storing a ''''0'''' is selected. When the bucket brigade sense amplifier is actuated, charge from the output capacitance thereof replenishes the bit line capacitance and leaves the output capacitance at a value of voltage approximately equal to one half of the charging voltage. In this manner, when a selected memory device associated with one half of a bit line is being read, the reference capacitance associated with the other half of the bit line is utilized to provide a voltage which is always the same regardless of the voltage on the selected device. The appropriate reference capacitor is selected by arranging the decoding such that when a memory device on one bit line half is selected, the reference capacitor on the other bit line half is always selected.
Inventors
- 👤 Y Yao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:00
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4099; G11C11/403; G11C11/404; G11C11/4091
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
319 words
A sense amplifier for sensing information in the form of stored charge comprising an amplifier responsive to differences in potential applied thereto, a pair of bit line elements electrically coupled to said amplifier, a plurality of first capacitances and second, third and fourth capacitances electrically coupled to each of said bit line elements, means connected to at least one of said plurality of first capacitances for setting said first capacitances in a charged or uncharged condition, said first capacitance being associated with one of said pair of bit line elements, means connected to said second and third capacitances of each of said pair of bit line elements and to said fourth capacitance of the other of said pair of bit line elements for charging said second and third capacitances up to approximately the same voltage and charging said fourth capacitance up to a voltage less than said same voltage, respectively, during a first portion of a sensing cycle, means interconnecting said first and second capacitances which are connected to said one bit line element and said second and fourth capacitances which are connected to said other bit line element actuable during a second portion of said sensing cycle for transferring or not transferring charge from said second to said first capacitance and for transferring charge from said second to said fourth capacitance, respectively, means interconnecting said second and third capacitances of said pair of bit line elements during a third portion of said sensine cycle for tranferring or not tranferring charge from said third capacitance to said second capacitance of said one of said pair of bit line elements and for transferring charge from said third to said second capacitance of the other of said pair of bit line elements, respectively, and means for electrically connecting said third capacitance of both of said pair of bit line elements to said amplifier during a fourth portion of said sensing cycle.
Claim 2
Dependent Claim
319 words
A sense amplifier for sensing information in the form of stored charge comprising an amplifier responsive to differences in potential applied thereto, a pair of bit line elements electrically coupled to said amplifier, a plurality of first capacitances and second, third and fourth capacitances electrically coupled to each of said bit line elements, means connected to at least one of said plurality of first capacitances for setting said first capacitances in a charged or uncharged condition, said first capacitance being associated with one of said pair of bit line elements, means connected to said second and third capacitances of each of said pair of bit line elements and to said fourth capacitance of the other of said pair of bit line elements for charging said second and third capacitances up to approximately the same voltage and charging said fourth capacitance up to a voltage less than said same voltage, respectively, during a first portion of a sensing cycle, means interconnecting said first and second capacitances which are connected to said one bit line element and said second and fourth capacitances which are connected to said other bit line element actuable during a second portion of said sensing cycle for transferring or not transferring charge from said second to said first capacitance and for transferring charge from said second to said fourth capacitance, respectively, means interconnecting said second and third capacitances of said pair of bit line elements during a third portion of said sensine cycle for tranferring or not tranferring charge from said third capacitance to said second capacitance of said one of said pair of bit line elements and for transferring charge from said third to said second capacitance of the other of said pair of bit line elements, respectively, and means for electrically connecting said third capacitance of both of said pair of bit line elements to said amplifier during a fourth portion of said sensing cycle.
Claim 3
Dependent Claim
61 words
A sense amplifier according to claim 1 wherein aid first capacitances are storage devices exhibiting capacitance, said second capacitance is the bit line capacitance of a bit line element, said third capacitance is a capacitor of substantialy the same capacitance as said first capacitance, and said fourth Capacitance is a storage device exhibiting a capacitance not more than said first capacitance.
Claim 4
Dependent Claim
79 words
A sense amplifier according to claim 2 wherein said means connected to at least one of said plurality of first capacitances for setting said first capacitance includes a first actuable gate disposed in series with said first capacitance, word line and bit line address decoders, the outputs of which are connected to word and bit line drivers, the coincidental occurrence of said outputs actuating said first actuable gate to set said first capacitance in a charge or uncharged condition.
Claim 5
Dependent Claim
100 words
A sense amplifier according to claim 3 wherein said means connected to said second and third capacitances of said pair of bit line elements and to said fourth capacitance of said other of said pair of bit line elements for charging includes sources of charging potential, second actuable gates connected between said sources and said third capacitances and between said sources and said second capacitances via third actuable gates and between one of said sources and said fourth capacitance of said other of said pair of bit lines via one of said third actuable gates and a fourth actuable gate.
Claim 6
Dependent Claim
38 words
An amplifier according to claim 4 wherein said means interconnecting said first and second capacitances and said second and fourth capacitances during a second portion of said sensing cycle are said first and said fourth actuable gates, respectively.
Claim 7
Dependent Claim
26 words
An amplifier according to claim 5 wherein said means interconnecting said second and third capacitances of said pair of bit lines is said third actuable gate.
Claim 8
Dependent Claim
44 words
An amplifier according to claim 6 wherein said means for electrically connecting said third capacitance of both of said pair of bit line elements to said amplifier includes a pulsed source connected to sad amplifier actuable during said fourth portion for enabling said amplifier.
Claim 9
Dependent Claim
25 words
An amplifier according to claim 6 wherein said fourth storage device is a capacitor exhibiting not less than one-half the capacitance of said first capacitance.
Claim 10
Dependent Claim
351 words
In a memory array for storing information in the form of charge on a plurality of stored charge memory devices connected to pairs of bit lines elements via actuable gating devices, said elements having an associated bit line capacitance a sense amplifier for sensing the charge condition of at least a selected one of said memory devices comprising: a reference charge storage device connected via a first actuable gate to each of said bit line elements, amplifier means hving first and second terminals responsive to a difference in voltage at said terminals, bucket brigade sense amplifier means having an output capacitance connected between each said terminal and a bit line element, charging means connected to each said bucket brigade amplifier means for charging said output capacitances and said bit line capacitances to approximately the same voltage and to one of said reference charge storage devices via said first actuable gate for charging said reference device to a voltage less than said same voltage, actuable pulsed sources connected to said gating device of said selected memory device and said actuable gate of said reference device for transferring charge from said bit line capacitance of one of said bit line elements when said memory device is empty of charge or transferring no charge when said memory device is filled with charge to charge up to or hold said memory device at said same voltage and for tranferring charge from said bit line capacitance of the other of said bit line elements to its associated reference device to charge it to said voltage less than said same voltage, and means connected to each of said bucket brigade amplifiers and said output capacitances for transferring a charged or uncharged condition from one output capacitance to said bit line capacitance of said one of said bit line elements and transferring a charged condition from the other of said output capacitances to said bit line capacitance of said other of said bit line elements to provide at one terminal said same voltage or zero voltage and at the other terminal said voltage less than said same voltage.
Claim 11
Dependent Claim
351 words
In a memory array for storing information in the form of charge on a plurality of stored charge memory devices connected to pairs of bit lines elements via actuable gating devices, said elements having an associated bit line capacitance a sense amplifier for sensing the charge condition of at least a selected one of said memory devices comprising: a reference charge storage device connected via a first actuable gate to each of said bit line elements, amplifier means hving first and second terminals responsive to a difference in voltage at said terminals, bucket brigade sense amplifier means having an output capacitance connected between each said terminal and a bit line element, charging means connected to each said bucket brigade amplifier means for charging said output capacitances and said bit line capacitances to approximately the same voltage and to one of said reference charge storage devices via said first actuable gate for charging said reference device to a voltage less than said same voltage, actuable pulsed sources connected to said gating device of said selected memory device and said actuable gate of said reference device for transferring charge from said bit line capacitance of one of said bit line elements when said memory device is empty of charge or transferring no charge when said memory device is filled with charge to charge up to or hold said memory device at said same voltage and for tranferring charge from said bit line capacitance of the other of said bit line elements to its associated reference device to charge it to said voltage less than said same voltage, and means connected to each of said bucket brigade amplifiers and said output capacitances for transferring a charged or uncharged condition from one output capacitance to said bit line capacitance of said one of said bit line elements and transferring a charged condition from the other of said output capacitances to said bit line capacitance of said other of said bit line elements to provide at one terminal said same voltage or zero voltage and at the other terminal said voltage less than said same voltage.
Claim 12
Dependent Claim
47 words
In a memory array a sense amplifier according to claim 9 further including means connected to said amplifier means for enabling it when said same voltage or zero voltage appears on said one terminal and said voltage less than said same voltage appears on said other terminal.
Claim 13
Dependent Claim
37 words
In a memory array a sense amplifier according to claim 10 further including means connected to said plurality of stored charge memory devices for setting at least one of said devices in a charged or uncharged condition.
Claim 14
Dependent Claim
70 words
In a memory array a sense amplifier according to claim 11 wherein said bucket brigade sense amplifiers includes a second actuable gate interconnecting said bit line capacitance and its output capacitance and, first and second pulsed voltage sources connected to said second actuable gate and to said output capacitance, respectively, said sources being actuated simultaneously to replenish or not replenish said bit line capacitance with charge from said output capacitance.
Claim 15
Dependent Claim
67 words
In a memory array a sense amplifier according to claim 12 wherein said means for setting includes an actuable gate disposed in series with each said memory device, word line and bit line decoders, the outputs of which are connected to word and bit line drivers, the coincidental occurrence of said outputs actuating said actuable gate to set said memory device in a charged or uncharged condition.
Claim 16
Dependent Claim
19 words
In a memory array a sense amplifier according to claim 13 wherein said amplifier means is a differential amplifier.
Claim 17
Dependent Claim
19 words
In a memory array a sense amplifier according to claim 13 wherein said amplifier means is a latch circuit.
Claim 18
Dependent Claim
58 words
In a memory array a sense amplifier according to claim 13 wherein said memory devices are devices exhibiting capacitance, said reference charge storage device is a device exhibiting capacitance not more than; the capacitance of said memory device and said output capacitance is a device exhibiting capacitance of approximatley equal value to the capacitance of said memory device.
Claim 19
Dependent Claim
321 words
A sense amplifier for sensing information in the form of stored charged comprising an amplifier responsive to differences in potential applied thereto, a pair of bit line elements electrically coupled to said amplifier, a plurality of first capacitances and second, third and fourth capacitance, electrically coupled to each of said bit line elements, means connected to at least one of said plurality of first capacitances and to said fourth capacitances for setting said first and said fourth capacitances in a charged and uncharged condition, said first capacitance and one of said fourth capacitances being associted with one of said pair of bit line elements, and the other of said fourth capacitances being associated with the other of said pair of bit line elements, means connected to said second and third capacitances of each of said pair of bit line elements for charging said second and third capacitances up to approximately the same voltage during a first portion of a sensing cycle, means interconnecting said first and second capacitances which are connected to said one line element and said second and fourth capacitances which are connected to said other bit line element actuable during a second portion of said sensing cycle for transferring or not transferring charge from said second to said first capacitance and for transferring charge from said second to said fourth capacitance, respectively, means interconnecting said second and third capacitances of, said pair of bit line elements during a third portion of said sensing cycle for transferring or not transferring charge from said third capacitance to said second capacitance of said one of said pair of bit line elements and for transferring charge from said third to said second capacitance of the other of said paIr of bit line elements, respectively, and means for electrically connecting said third capacitance of both of said pair of bit line elements to said amplifier during a fourth portion of said sensing cycle.
Claim 20
Dependent Claim
321 words
A sense amplifier for sensing information in the form of stored charged comprising an amplifier responsive to differences in potential applied thereto, a pair of bit line elements electrically coupled to said amplifier, a plurality of first capacitances and second, third and fourth capacitance, electrically coupled to each of said bit line elements, means connected to at least one of said plurality of first capacitances and to said fourth capacitances for setting said first and said fourth capacitances in a charged and uncharged condition, said first capacitance and one of said fourth capacitances being associted with one of said pair of bit line elements, and the other of said fourth capacitances being associated with the other of said pair of bit line elements, means connected to said second and third capacitances of each of said pair of bit line elements for charging said second and third capacitances up to approximately the same voltage during a first portion of a sensing cycle, means interconnecting said first and second capacitances which are connected to said one line element and said second and fourth capacitances which are connected to said other bit line element actuable during a second portion of said sensing cycle for transferring or not transferring charge from said second to said first capacitance and for transferring charge from said second to said fourth capacitance, respectively, means interconnecting said second and third capacitances of, said pair of bit line elements during a third portion of said sensing cycle for transferring or not transferring charge from said third capacitance to said second capacitance of said one of said pair of bit line elements and for transferring charge from said third to said second capacitance of the other of said paIr of bit line elements, respectively, and means for electrically connecting said third capacitance of both of said pair of bit line elements to said amplifier during a fourth portion of said sensing cycle.
Claim 21
Dependent Claim
14 words
A sense amplifier according to claim 17 wherein said amplifier is a differential amplifier.
Claim 22
Dependent Claim
14 words
A sense amplifier according to claim 17 wherein said amplifier is a latch circuit.
Claim 23
Dependent Claim
27 words
A sense amplifier according to claim 17 further including charging means connected to said fourth capacitances for charging them during an interval outside of said sensing cycle.
Claim 24
Dependent Claim
61 words
A sense amplifier according to claim 17 wherein said first capacitances are storage devices exhibiting capacitance, said second capacitance is the bit line capacitance of a bit line element, said third capacitance is a capacitor of substantially the same capacitance as said first capacitance, and said fourth capacitancee is a storage device exhibiting a capacitance not greater than said first capacitance.
Claim 25
Dependent Claim
25 words
An amplifier according to claim 21 wherein said fourth storage device is a capacitor exhibiting not less than one-half the capacitance of said first capacitance.
Claim 26
Dependent Claim
79 words
A sense amplifier according to claim 17 wherein said means connected to at least one of said plurality of first capacitances for setting said first capacitance includes a first actuable gate disposed in series with said first capacitance, word line and bit line address decoders, the outputs of which are connected to word and bit line drivers, the coincidental occurrence of said outputs actuating said first actuable gate to set said first capacitance in a charged or uncharged condition.
Claim 27
Dependent Claim
52 words
A sense amplifier according to claim 23 wherein said means connected to said second and third capacitances of said pair of bit line elements includes sources of charging potential, second actuable gates connectee between said sources and said third capacitances and between said sources and said second capacitances via third actuable gates.
Claim 28
Dependent Claim
38 words
An amplifier according to claim 24 wherein said means interconnecting said first and second capacitances and said second and fourth capacitance during a second portion of said sensing cycle are said first and said fourth actuable gates, respectively.
Claim 29
Dependent Claim
26 words
An amplifier according to claim 25 wherein said measn interconnecting said second and third capacitances of said pair of bit lines is said third actuable gate.
Claim 30
Dependent Claim
44 words
An amplifier according to claim 26 wherein said means for electrically connecting said third capacitance of both of said pair of bit line elements to said amplifier includes a pulsed source connected to said amplifier actuable during said fourth portion for enabling said amplifier.
Claim 31
Dependent Claim
12 words
An amplifier according to claim 27 wherein said first capacitances are capacitors.
Claim 32
Dependent Claim
19 words
An amplifier according to claim 28 wherein said first, second, third and fourth actuable gates are field effect transistors.
Claim 33
Dependent Claim
39 words
An amplifier according to claim 29 wherein said first actuable gate is a field effect transistor, the gate of which is connected to said word line driver and another terminal of which is connected to said bit line driver.
References Cited (Backward Citations)
US3514765A
Cited
US3665422A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-17 | 1977-03-19 | 1977-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-17 | 1981-03-19 | 1981-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-17 | 1985-03-19 | 1985-09-18 | $7700.00 | Window Closed / Lapsed |