US3665422A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit,random access memory
Assignee: Electronic Arrays Inc
•
Filing: 1970-01-26
•
Granted: 1972-05-23
•
Expires: 1990-01-26
Abstract
Abstract An integrated circuit MOS type memory is disclosed operating with two phases and minimum component cells. The cells are respectively located at intersections of a pair of two phase operated addressing lines and of a set of data write and read lines synchronously operated with addressing. Read addressing of cells in controlled concurrently with address decoding; write addressing of memory cells is dependent upon preceding read addressing of the same cells and concurs with preparation for the next addressing operation. Memory read lines are kept at floating potential prior to reading addressed cells which control the respective read lines to obtain node discharge or no-discharge in refresher amplifiers. Refresh write operations are controlled during the respective next write phase in dependence upon the charge contents of the nodes in the refresher amplifiers.
Inventors
- 👤 Michael R Mccoy
- 👤 Terry R Walther
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/403; G11C11/405; G11C11/4063; G11C11/407; G11C11/409
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
386 words
In an integrated circuit memory operating in response to first and second alternating phase signals and in further response to digital addressing signals, comprising: decoder means connected to receive the first and second phase signals and to receive the addressing signals and providing a pair of sequential addressing outputs respectively during a first, and a succeeding second phase signal for each digital signal received during a first phase signal; a plurality of data-read-lines, one per bit position within a chosen multi bit word format, there being as many data lines as a word has bit positions; a plurality of memory cells to the bit level and organized to the word level, each memory location to the word level having as many cells as the plurality of word has bits, the cells of the plurality pertaining to the same memory location to the word level connected to receive a pair of said outputs as provided in response to a digital signal representing the address of the word, each memory cell having a storage node; first means included in each memory cell to control voltage in the respective data read line in response to a first phase addressing output of the pair as provided by the decoder means, when received by the cell, and in dependence upon the charge level in the storage node of the respective cell; a plurality of second means respectively connected to the data read lines of the plurality and each including a node the voltage thereof controlled by the respective date read line during a first phase signal independently from addressing signals, each of the second means provided for refreshrecycling data of all memory cells connected to the respective data read line, one at a time, as addressed by a first phase addressing output; a plurality of data-write-lines, one per bit position; third means included in each memory cell to connect operatively the storage node thereof to the respective data write line of the plurality in response to a second phase addressing output of the pair as provided in the decoder means; and fourth means included in each of the plurality of second means and connected to be responsive to the undecoded second phase signals to couple the respective node of the second means to the respective data write line in response thereto.
Claim 2
Dependent Claim
386 words
In an integrated circuit memory operating in response to first and second alternating phase signals and in further response to digital addressing signals, comprising: decoder means connected to receive the first and second phase signals and to receive the addressing signals and providing a pair of sequential addressing outputs respectively during a first, and a succeeding second phase signal for each digital signal received during a first phase signal; a plurality of data-read-lines, one per bit position within a chosen multi bit word format, there being as many data lines as a word has bit positions; a plurality of memory cells to the bit level and organized to the word level, each memory location to the word level having as many cells as the plurality of word has bits, the cells of the plurality pertaining to the same memory location to the word level connected to receive a pair of said outputs as provided in response to a digital signal representing the address of the word, each memory cell having a storage node; first means included in each memory cell to control voltage in the respective data read line in response to a first phase addressing output of the pair as provided by the decoder means, when received by the cell, and in dependence upon the charge level in the storage node of the respective cell; a plurality of second means respectively connected to the data read lines of the plurality and each including a node the voltage thereof controlled by the respective date read line during a first phase signal independently from addressing signals, each of the second means provided for refreshrecycling data of all memory cells connected to the respective data read line, one at a time, as addressed by a first phase addressing output; a plurality of data-write-lines, one per bit position; third means included in each memory cell to connect operatively the storage node thereof to the respective data write line of the plurality in response to a second phase addressing output of the pair as provided in the decoder means; and fourth means included in each of the plurality of second means and connected to be responsive to the undecoded second phase signals to couple the respective node of the second means to the respective data write line in response thereto.
Claim 3
Dependent Claim
66 words
In an integrated circuit as in claim 1, there being means connecting the data read lines of the plurality to a source of reference potential during each second phase signal, the data read line having essentially floating potential immediately prior to a second phase signal by operation of which a node of a cell of the plurality controls the voltage of the respective data read line.
Claim 4
Dependent Claim
85 words
In an integrated circuit as in claim 1, the second means of the plurality including means defining a second node capable of holding a charge, a first transistor connected to control discharge of the second node in response to the potential of the respective data read line; a second transistor operating in response to first phase signals to couple the second node to the first node; and a third transistor connected for charging the second node during and in response to each second phase signals.
Claim 5
Dependent Claim
69 words
In an integrated circuit as in claim 1 and including means for charging each of the data write lines of the plurality, effective as a node, for receiving a charge in response to each undecoded first phase signal, the respectively associated fourth means operating to discharge or to maintain the charge of the latter node in response to the charge content of the node included in the second means.
Claim 6
Dependent Claim
110 words
In an integrated circuit memory as in claim 1, the decoder means including, for each address as identified by differing addressing signals, a plurality of transistors having gate electrodes connected to receive the digital signals, further having interconnected first main electrodes, and having second maIn electrodes connected to a source of reference potential; means for each address establishing a node, and connected for being charged in response to a second phase signal and discharged in response to a first phase signal and through any of the transistors of the plurality when conductive; and circuit means connected for deriving the pair of gating signals from the charge state of that node.
Claim 7
Dependent Claim
137 words
In an integrated circuit memory as in claim 1, the decoder means including, for each address, means for providing a particular logic signal in response to a particular digital addressing signal; first transistor means and a second transistor, the first transistor means having electrode defining means connected between the gate of the second transistor and the means for providing the particular logic signal, the second transistor having a capacitor connected between its source electrodes and its gate, the first phase signal being applied to the first transistor means, the second phase signal being applied to the drain electrode of the second transistor, the first one of the gating outputs being derived from the source electrode of the first transistor, the memory cells pertaining to the same address connected to receive the one gating output for read addressing.
Claim 8
Dependent Claim
67 words
In an integrated circuit memory as in claim 6, the first transistor means including a third transistor and a fourth transistor, the third transistor having its main electrodes connected between the gate of the second transistor and a source for a logic signal, the fourth transistor also connected to the gate of the second transistor to provide a charge thereto in response to each second phase signal.
Claim 9
Dependent Claim
102 words
In an integrated circuit memory as in claim 6, including a third and a fourth transistor, the gate of the third transistor and one main electrode of the fourth transistor connected to respectively receive the first and second phase signals, one main electrode of the third transistor connected to receive the one gating output and having its other main electrode connected to the gate of the fourth transistor, a feedback capacitor connected between the gate and the source electrode of the fourth transistor, the second one of the pair of gating outputs being derived from the source electrode of the fourth transistor.
Claim 10
Dependent Claim
110 words
In an integrated circuit memory as in claim 1, the first means in each memory cell being a first field effect transistor, the third means being a second field effect transistor, the second transistor connecting directly the respective data write line to the node, the first transistor having its gate connected to directly the node and its source electrode connected directly to the data read line, the drain electrode of the first transistor connected to receive operating potential during each decoded first phase signal, the gate of the second transistor connected to receive each decoded second phase signal, and a capacitor connected between the data read line and the node.
Claim 11
Dependent Claim
177 words
In an integrated circuit memory as in claim 9, a plurality of third field effect transistors connected to discharge the data read lines of the plurality and to provide thereto reference potential during and in response to each second phase signal, the respective second transistors charging the data lines when rendered conductive during first phase signals in dependence upon the charge state of the node in the respective cell; a plurality of fourth field effect transistors connected to charge the data write lines of the plurality during and in response to each first phase signal; the second means respectively connected to control discharge of the data write lines in response to the charge state of the respective node in the second means as was established during a first phase and in response to and during the succeeding second phase signal, the second means further connected to control the charge state of the node in the second means in response to a voltage drop from reference potential of the respective data read line duriNg a first phase signal.
Claim 12
Dependent Claim
197 words
In an integrated circuit memory as in claim 1, the first means in each memory cell including a field effect transistor having its gate connected to the node in the cell, its drain electrode connected to receive operating voltage when the cell is accessed during a first phase, the source electrode of the first transistor connected to the data read line; a plurality of field effective transistors, not pertaining to any cell, respectively connected to the data read lines of the plurality, to discharge the data read lines to reference potential in response to each second phase signal and maintaining the data read lines at floating potential in between; a plurality of field effective transistors, one in each of the seconds means, respectively having its gate connected to the respective data read line and connected with drain and source electrodes between the node of the second means and a source of reference potential to discharge the node when the voltage of the data read line falls from the reference potential level by operation of said transistor in the cell, there being means to charge the node of the second means in response to each second phase signal.
Claim 13
Dependent Claim
79 words
In a memory as in claim 11, each cell including a second field effect transistor connected directly with its drain and source electrodes respectively between the respective data write line and the node in the cell, the source electrode of the second transistor and the gate electrode of the transistor of the first means establishing the node of the cell, the gate electrode of the second transistor connected to receive the second phase addressing output of the decoder outputs.
Claim 14
Dependent Claim
67 words
In a memory as in claim 12 and including means for charging each of the data write lines of the plurality, effective as a node, for receiving a charge in response to each undecoded first phase signal, the respectively associated fourth means operating to discharge or to maintain charge of the latter node in response to the charge content of the node included in the second means.
Claim 15
Dependent Claim
252 words
In an integrated memory having addressable storage locations to the bit level, further having data bit read lines, an addressed bit location provided to set a bit into one of the data bit write lines, an addressed bit location provided to receive and store a bit set into one of the data bit write lines, a bit location being connected to a data bit read line and to a data bit write line, the combination for a bit location comprising: a first and a second field effect transistor connected in series to each other, the second transistor connected with one of its main electrodes to the data bit read line; a third field effect transistor connected with its main electrodes between the write line and the gate electrode of the second transistor, the latter connection establishing a capacitive storage node; a read-addressing line connected to the gate of the first transistor to render the first transistor conductive when receiving a read-addressing signal; a write-addressing line connected to the gate electrode of the third transistor to render the transistor conductive when receiving a write-addressing signal; and circuit means connected to the first transistor for rendering the first transistor conductive upon a particular signal in the write-addressing line, to establish signal level at the interconnection of the first and second transistor permitting the second transistor to become conductive, depending upon the charge state of said node. the other main electrode being connected to the second transistor and the gate connected to the read-addressing line.
Claim 16
Dependent Claim
252 words
In an integrated memory having addressable storage locations to the bit level, further having data bit read lines, an addressed bit location provided to set a bit into one of the data bit write lines, an addressed bit location provided to receive and store a bit set into one of the data bit write lines, a bit location being connected to a data bit read line and to a data bit write line, the combination for a bit location comprising: a first and a second field effect transistor connected in series to each other, the second transistor connected with one of its main electrodes to the data bit read line; a third field effect transistor connected with its main electrodes between the write line and the gate electrode of the second transistor, the latter connection establishing a capacitive storage node; a read-addressing line connected to the gate of the first transistor to render the first transistor conductive when receiving a read-addressing signal; a write-addressing line connected to the gate electrode of the third transistor to render the transistor conductive when receiving a write-addressing signal; and circuit means connected to the first transistor for rendering the first transistor conductive upon a particular signal in the write-addressing line, to establish signal level at the interconnection of the first and second transistor permitting the second transistor to become conductive, depending upon the charge state of said node. the other main electrode being connected to the second transistor and the gate connected to the read-addressing line.
Claim 17
Dependent Claim
35 words
In a memory as in claim 14, there being a fourth transistor connected to the read line to discharge the read line prior to each read addressing of the cell relative to a reference potential.
Claim 18
Dependent Claim
146 words
In a memory as in claim 16, there being a fifth and a sixth field effect transistor respectively having connected source-to-drain electrodes to establish a nOde external to the cell. The source electrode of the sixth transistor connected to the source of reference potential, the gate of the sixth transistor connected to the read line to be rendered conductive when the voltage of the read line relative to ground exceeds threshhold of response for the sixth transistor during read addressing of the cell, the fifth transistor charging said external node to potential prior to read addressing of the cell, the node external to the cell being discharged when the sixth transistor is conductive, and circuit means for controlling the voltage of the write line in dependence upon the charge state of the node external to the cell and as established during read addressing of the cell.
Claim 19
Dependent Claim
97 words
In a memory as in claim 14, a fourth and a fifth field effect transistor having source-to-drain connected electrodes, the source electrode of the fifths transistor connected to a source of reference potential, the source electrode of the fourth transistor connected to the write line; the sixth transistor operating to establish a charge potential different from ground in the write line prior to each write addressing of the cell; and circuit means connected for copying and logically inverting the copied charge content of the node and applying a corresponding charge to the gate of the fifth transistor.
Claim 20
Dependent Claim
329 words
In an integrated circuit memory having a plurality of addresable locations for storage to the word level, a word defined by a plurality of bits, each location to the word level connected to operate in response to read-addressing signals and write-addressing signals, a read addressing signal being provided when read-out of the content of a storage location to the word level is desired, a write-addressing signal being provided when storage of a word in a location to the word level is desired, the memory further responsive to digital addressing signals for addressing a storage location, the memory further operating in response to first phase signals for read control and second phase signals for write control produced in alternating sequence, the combination comprising: first means respectively pertaining to a memory location of the plurality for providing a logic signal in response to first phase signals and in further response to the digital addressing signals when addressing the location; a first field effect transistor having a drain electrode connected to receive the first phase signal, having a gate electrode connected to the first means to receive the logic signal and having a source electrode connected to provide a read-addressing signal for the memory location in dependence upon the state of conduction of the first transistor; a capacitor connected between gate and source electrodes to provide positive feedback; a second transistor having a drain electrode connected to the source of the first transistor, a gate electrode connected to receive the first phase signals, ahd having a source electrode; a third transistor having a drain electrode connected to receive the second phase signals, having a gate electrode connected to the source electrode of the second transistor to establish a node therewith charged in dependence upon the state of conduction of the first transistor, and having a source electrode providing the write-addressing signal for the memory; and a capacitor connected between said source and gate electrodes of the third transistor to provide positive feedback.
Claim 21
Dependent Claim
329 words
In an integrated circuit memory having a plurality of addresable locations for storage to the word level, a word defined by a plurality of bits, each location to the word level connected to operate in response to read-addressing signals and write-addressing signals, a read addressing signal being provided when read-out of the content of a storage location to the word level is desired, a write-addressing signal being provided when storage of a word in a location to the word level is desired, the memory further responsive to digital addressing signals for addressing a storage location, the memory further operating in response to first phase signals for read control and second phase signals for write control produced in alternating sequence, the combination comprising: first means respectively pertaining to a memory location of the plurality for providing a logic signal in response to first phase signals and in further response to the digital addressing signals when addressing the location; a first field effect transistor having a drain electrode connected to receive the first phase signal, having a gate electrode connected to the first means to receive the logic signal and having a source electrode connected to provide a read-addressing signal for the memory location in dependence upon the state of conduction of the first transistor; a capacitor connected between gate and source electrodes to provide positive feedback; a second transistor having a drain electrode connected to the source of the first transistor, a gate electrode connected to receive the first phase signals, ahd having a source electrode; a third transistor having a drain electrode connected to receive the second phase signals, having a gate electrode connected to the source electrode of the second transistor to establish a node therewith charged in dependence upon the state of conduction of the first transistor, and having a source electrode providing the write-addressing signal for the memory; and a capacitor connected between said source and gate electrodes of the third transistor to provide positive feedback.
Claim 22
Dependent Claim
56 words
In a memory as in claim 19, the first means including a fourth transistor connected to charge a node as established with the gate of the first transistor in response to each second phase signal, and a fifth transistor responsive to the digital addressing signals and selectively controlling discharge of the node during first phase signals.
Claim 23
Dependent Claim
131 words
In an integrated circuit memory as in claim 19, the memory location comprising a plurality of bit cells, each comprising a storage node and a transistor having its gate connected to the storage node; means fOr causing operating potential applied to the drain electrodes of the transistors in the bit cells in response to a read-addressing signal; a feedback capacitor in each cell connected between the source electrode of the transistor in the cell and the node thereof; and a plurality of data read lines at floating potential respectively connected to the source electrodes of the transistors of the cells, the voltage of the data read lines being controlled in dependence upon the nodes and in response to a read-addressing signal as produced at the time of a first phase signal.
Claim 24
Dependent Claim
47 words
In a circuit as in claim 21, each cell including another transistor having source electrode connected to the node in the cell, drain electrode connected to receive data write signal, and having its gate connected to receive the write addressing signal as provided by the third transistor.
Claim 25
Dependent Claim
61 words
In a circuit as in claim 19, and including second means connected for operation in parallel to the first means, and coupled to the source electrode of the first transistor to apply non-addressing potential to the memory location connected to receive the read-addressing signal, if the first and second means receive addressing signals different from the ones required for addressing response.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-23 | 1975-11-22 | 1976-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-23 | 1979-11-22 | 1980-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-23 | 1983-11-22 | 1984-05-23 | $7700.00 | Window Closed / Lapsed |