Charge coupled shift registers

Claim 2

In combination: a pair of multiple stage charge-coupled shift registers; means for concurrently shifting charge signals through one of said registers and complements of these charge signals through the other of said registers; and a differential signal detector coupled at one input terminal to a stage of one of said registers and at its other input terminal to a corresponding stage of the other of said shift registers.

Claim 3

In the combination as set forth in claim 1, each register comprising a semiconductor substrate and successive electrodes capacitively coupled to said substrate, and the stage in each register to which said signal detector is coupled comprising an electrically floating region in said substrate of different conductivity than the substrate located adjacent to one of the electrodes of said register.

Claim 4

In the combination as set forth in claim 2, said signal detector comprising a four-transistor flip-flop, each said transistor having a source electrode, a drain electrode and a control electrode, said regions in said substrate serving as the respective source electrodes for the first and second of said transistors, respectively.

Claim 5

In the combination as set forth in claim 3, further including a third region in said substrate of different conductivity than said substrate serving as a common drain electrode, and control electrode means spaced from said substrate and extending between the source electrode of said first transistor and said third region and between the source electrode of said second transistor and said third region.

Claim 6

In the combination as set forth in claim 1, said charge-coupled, shift registers comprising a common substrate, a relatively thin insulating film over one region of said substrate a relatively thin insulating film over a second region of said substrate; a relatively thick insulating film over a third region of the substrate between said first and second regions and, at each stage of each register, electrode means spaced from and capacitively coupled to the substrate by the relatively thin film, passing over the relatively thick film and forming over the other relatively thin film the electrode means of a corresponding stage of the other register.

Claim 7

In a charge coupled circuit, in combination: a semiconductor substrate of one conductivity type; first, second and third spaced regions in said substrate, all of different conductivity type than said substrate, said first and third regions comprising electrically floating regions; a minority carrier surface charge signal storage location; a first electrode capacitively coupled to the substrate, to said location, and to said first region for transferring the minority carrier surface charge at said location to said first region; a second electrode capacitively coupled to the region of said substrate between said first and second regions, responsive to a signal for removing charge from said first to said second region and for resetting said first region to a reference potential; a second minority carrier surface charge signal storage location; a third electrode capacitively coupled to the substrate to said second location and to said third region for transferring the minority carrier surface charge at said second location to said third region; a fourth electrode extending between said second and third regions and capacitively coupled to the portion of the substrate extending between these regions responsive to a signal for resetting said third region to said reference potential; two output terminals, one coupled to said first region and the other coupled to said third region; and a differential signal detection circuit having two input terminals coupled to said two output terminals, respectively.

Claim 8

In a charge coupled circuit, in combination: a semiconductor substrate of one conductivity type; first, second and third spaced regions in said substrate, all of different conductivity type than said substrate, said first and third regions comprising electrically floating regions; a minority carrier surface charge signal storage location; a first electrode capacitively coupled to the substrate, to said location, and to said first region for transferring the minority carrier surface charge at said location to said first region; a second electrode capacitively coupled to the region of said substrate between said first and second regions, responsive to a signal for removing charge from said first to said second region and for resetting said first region to a reference potential; a second minority carrier surface charge signal storage location; a third electrode capacitively coupled to the substrate to said second location and to said third region for transferring the minority carrier surface charge at said second location to said third region; a fourth electrode extending between said second and third regions and capacitively coupled to the portion of the substrate extending between these regions responsive to a signal for resetting said third region to said reference potential; two output terminals, one coupled to said first region and the other coupled to said third region; and a differential signal detection circuit having two input terminals coupled to said two output terminals, respectively.

Claim 9

In a charge-coupled circuit as set forth in claim 6, further including: a fourth region in said substrate of different conductivity than said substrate, said fourth region serving as a source of minority charge carriers; means creating a potential well at a region of said substrate close to said fourth region; and a control fifth electrode coupled to the region of said substrate between said fourth region and said means creating a potential well and connected to one of said output terminals, said fourth electrode for controlling the flow of charge from said fourth region to said potential well.

Claim 10

In a charge-coupled circuit as set forth in claim 7, further including a control sixth electrode coupled to the region of said substrate between said fourth region and said means creating a potential well.

Claim 11

In a charge-coupled circuit as set forth in claim 8, said fifth and sixth electrodes comprising two overlapping electrodes for creating in said substrate two conduction paths, in series, between said fourth region and said potential well.

Claim 12

In a charge-coupled circuit as set forth in claim 7, further including: means creating a second potential well at another region of said substrate close to said fourth region; and another control electrode, this one coupled to the region of said substrate between said fourth region and said second potential well and connected to the other of said output terminals.

Claim 13

In combination: a semiconductor substrate of one conductivity type; a first charge-coupled shift register integrated into said substrate and including an output terminal; and a second charge-coupled shift register integrated into said substrate comprising: a first source of minority carriers at one region of the substrate; a second source of minority carriers at a second region of said substrate; a storage electrode close to both of said sources and spaced a small distance from said substrate for creating a potential well in the region of the substrate beneath said storage electrode; first control means at least one portion of which is coupled to said input terminal for controlling the flow or charge from said first source to said potential well in accordance with the signals produced at said output terminal; second control means at least one portion of which is responsive to external signals for controlling the flow of charge from said second source to said first potential well; and means coupled to another portion of said first and second control means for concurrently causing one to prevent the passage of charge carriers and the other to permit the passage of charge carriers.

Claim 14

In combination: a semiconductor substrate of one conductivity type; a first charge-coupled shift register integrated into said substrate and including an output terminal; and a second charge-coupled shift register integrated into said substrate comprising: a first source of minority carriers at one region of the substrate; a second source of minority carriers at a second region of said substrate; a storage electrode close to both of said sources and spaced a small distance from said substrate for creating a potential well in the region of the substrate beneath said storage electrode; first control means at least one portion of which is coupled to said input terminal for controlling the flow or charge from said first source to said potential well in accordance with the signals produced at said output terminal; second control means at least one portion of which is responsive to external signals for controlling the flow of charge from said second source to said first potential well; and means coupled to another portion of said first and second control means for concurrently causing one to prevent the passage of charge carriers and the other to permit the passage of charge carriers.

Claim 15

In the combination as set forth in claim 11, further including means maintaining both of said sources at the same potential.

Claim 16

In the combination as set forth in claim 12, further including a third charge-coupled shift register integrated into said substrate, and means responsive to the charge signal present at said output terminal for controlling the introduction of charge into said third charge-coupled shift register.

Claim 17

In the combination as set forth in claim 1, said differential signal detector comprising a balanced detector.

Claim 18

In the combination as set forth in claim 14, said balanced detector comprising a flip flop which is normally in the inactive, that is, the non-storage state, said flip flop including at each of its input terminals, means for storing a charge signal when in its inactive stage, and further including means for activating said flip flop after receipt of charge signal, the state said flip flop assumes, when activated, depending upon the relative charges stored at said two input terminals when said flip flop is in its inactive state.