US3987418A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chip topography for MOS integrated circuitry microprocessor chip
Assignee: Motorola Solutions Inc
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Filing: 1974-10-30
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Granted: 1976-10-19
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Expires: 1994-10-30
Abstract
Abstract The chip architecture of an MOS microprocessor chip includes data bus input-output buffer circuitry located along the lower right hand edge of the chip. High order address buffer output circuitry is located along the bottom of the chip. Directly to the left of the data bus input-output buffer circuitry is the arithmetic logic unit circuitry, and to the right of this and adjacent to the high order address bit buffer circuitry is located a register section including first accumulator register, a second accumulator register, high and low order index registers, a high order incrementer and an associated program counter, a low order incrementer and associated program counter, a high order stack pointer register and a low order stack pointer register, and a temporary register arranged on the surface of the microprocessor chip in a particular sequence. To the left of the register section and along the lower left hand edge of the chip is located a plurality of low order address bit buffer circuits. Above and coupled to the register section and to the arithmetic logic unit is located a plurality of bootstrap driver circuits for driving signals which enable programmed data transfers between the various registers, the arithmetic logic unit and a plurality of internal data bus and address bus conductors coupled to the data bus input-output buffer circuitry and the high order and the low order address bit buffer circuits, respectively. Read/write circuitry, a condition code register, decision logic circuitry, and an instruction register are located in sequence along the upper righthand edge of the chip. To the left of the decision logic circuitry and the condition code register and above the bootstrap driver circuitry and coupled thereto is a logic control circuitry section. Above the logic control circuitry and along the upper edge of the chip to the left of the instruction register is located an instruction decoder circuitry section. Along the upper lefthand edge of the chip is located input-output control circuitry and look-ahead circuitry for the instruction decoder. Between the lefthand portion of the logic control circuitry and the right hand portion of the I/O control circuitry is located timing generator circuitry coupled to the logic control circuitry for enabling the selected logic gates therein, which are selected and driven by the instruction decoder.
Inventors
- 👤 John K. Buchanan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:53
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
281 words
An integrated circuit microprocessor chip having first, second, third and fourth edges and a surface comprising: data bus means on said surface for transferring digitial data; address bus means on said surface for transferring digital address information; register circuit means on said surface coupled to said data bus means and said address bus means for storing digital information received from said data bus means and said address bus means and transferring digital information to and from said data bus means and said address bus means in accordance with execution of program instructions by said integrated circuit microprocessor chip, said register circuit means being located closer to said first and second edges than to said third and fourth edges; address output buffer circuit means on said surface coupled to said address bus means for temporarily storing digital address information and transmitting said digital address information from said integrated circuit microprocessor chip, said address output buffer circuit means being located along said first and second edges between said first and second edges and said register circuit means; data input-output buffer circuit means on said surface coupled to said data bus means for tranferring said digital data to and from said integrated circuit microprocessor chip; logic control circuit means on said surface located along and spaced from said register circuit means coupled to said input-output buffer circuit means for generating a plurality of control signals for controlling transfers of data within said integrated circuit microprocessor chip; and driver circuit means on said surface coupled between said register circuit means and said logic control circuit means for enabling data transfer between said register circuit means and said address bus means and said data bus means.
Claim 2
Dependent Claim
281 words
An integrated circuit microprocessor chip having first, second, third and fourth edges and a surface comprising: data bus means on said surface for transferring digitial data; address bus means on said surface for transferring digital address information; register circuit means on said surface coupled to said data bus means and said address bus means for storing digital information received from said data bus means and said address bus means and transferring digital information to and from said data bus means and said address bus means in accordance with execution of program instructions by said integrated circuit microprocessor chip, said register circuit means being located closer to said first and second edges than to said third and fourth edges; address output buffer circuit means on said surface coupled to said address bus means for temporarily storing digital address information and transmitting said digital address information from said integrated circuit microprocessor chip, said address output buffer circuit means being located along said first and second edges between said first and second edges and said register circuit means; data input-output buffer circuit means on said surface coupled to said data bus means for tranferring said digital data to and from said integrated circuit microprocessor chip; logic control circuit means on said surface located along and spaced from said register circuit means coupled to said input-output buffer circuit means for generating a plurality of control signals for controlling transfers of data within said integrated circuit microprocessor chip; and driver circuit means on said surface coupled between said register circuit means and said logic control circuit means for enabling data transfer between said register circuit means and said address bus means and said data bus means.
Claim 3
Dependent Claim
28 words
An integrated circuit microprocessor chip as recited in claim 1 wherein said first, second third, and fourth edges circumscribe said integrated circuit microprocessor chip in a clock-wise sequence.
Claim 4
Dependent Claim
45 words
An integrated circuit microprocessor chip as recited in claim 1 further including arithmetic logic unit circuit means on said surface located between said register circuit means and said fourth edge coupled to said data bus means and said address bus means for performing digital computations.
Claim 5
Dependent Claim
104 words
An integrated circuit microprocessor chip as recited in claim 3 wherein said logic control circuit means includes instruction decoder circuit means for decoding an instruction to be executed by said integrated circuit microprocessor chip and generating a plurality of control signals, and also includes look-ahead circuit means for precharging conductors of said instruction decoder means coupled to said instruction decoder means and said data input-output buffer circuit means, said instruction decoder means being located closer to said third edge than to said driver circuit means, said look-ahead means being located closer to said second and third edges than to said first and fourth edges.
Claim 6
Dependent Claim
41 words
An integrated circuit microprocessor chip as recited in claim 4 further including instruction register circuit means coupled between said instruction decoder circuit means and said data input-output buffer circuit means located between said fourth edge and said instruction decoder circuit means.
Claim 7
Dependent Claim
42 words
An integrated circuit microprocessor chip as recited in claim 4 further including timing control circuit means located along said second edge adjacent said said logic control circuit means for generating enable signals to effect data transfers in said integrated circuit microprocessor chip.
Claim 8
Dependent Claim
79 words
An integrated circuit microprocessor chip as recited in claim 4 further including a condition control register circuit means located in said logic control circuit means between said arithmetic logic unit circuit means and said instruction register circuit means along said fourth edge and coupled to said data bus means for storing data in response to signals from said data input-output buffer circuit means to enable signal propagation from said instruction register circuit means through said control logic circuit means.
Claim 9
Dependent Claim
52 words
The integrated circuit microprocessor chip as recited in claim 7 further including read/write circuit means coupled between said condition code register circuit means and said data input-output buffer circuit means coupled to said logic control circuit means for controlling whether said integrated circuit microprocessor chip undergoes a read or a write operation.
Claim 10
Dependent Claim
192 words
An integrated circuit microprocessor having first, second, third, and fourth edges and a surface comprising: data bus means; address bus means; a plurality of storage means for storing data coupled to said data bus means and said address bus means, said plurality of register means being located on said surface closer to said first and second edges than to said third and fourth edges; data input-output circuit means coupled to said data bus means for transferring data to and from said integrated circuit microprocessor, said data input-output circuit means being located substantially along said fourth edge and substantially adjacent and spaced from said storage means; address output circuit means coupled to said address bus means for transmitting digital address information from said integrated circuit microprocessor located substantially adjacent said second edge between said second edge and said storage means; and control circuit means coupled to said storage means and said data input-output circuit means for controlling data transfers between said storage means and said data bus means, said address bus means, and said input-output circuit means, said control circuit means being located substantially between said register circuit means and said third edge.
Claim 11
Dependent Claim
192 words
An integrated circuit microprocessor having first, second, third, and fourth edges and a surface comprising: data bus means; address bus means; a plurality of storage means for storing data coupled to said data bus means and said address bus means, said plurality of register means being located on said surface closer to said first and second edges than to said third and fourth edges; data input-output circuit means coupled to said data bus means for transferring data to and from said integrated circuit microprocessor, said data input-output circuit means being located substantially along said fourth edge and substantially adjacent and spaced from said storage means; address output circuit means coupled to said address bus means for transmitting digital address information from said integrated circuit microprocessor located substantially adjacent said second edge between said second edge and said storage means; and control circuit means coupled to said storage means and said data input-output circuit means for controlling data transfers between said storage means and said data bus means, said address bus means, and said input-output circuit means, said control circuit means being located substantially between said register circuit means and said third edge.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-10-19 | 1980-04-19 | 1980-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-10-19 | 1984-04-19 | 1984-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-10-19 | 1988-04-19 | 1988-10-19 | $7700.00 | Window Closed / Lapsed |