Selective retrieval and memory system

Claim 2

A selection and memory system for use in an automatic phonograph or the like, for selectively re-trieving data respectively stored at different storage addresses of a shift register memory, said system comprising: means for writing data in said memory at an address corresponding to an encoded selection input signal, said storage means comprising means for storing an address information signal defining a stage of said register corresponding to the selection signal interrogating means for sequentially reading out the storage addresses of said memory by successively shifting a shift register thereof, a counter for storing the status of said shift register, means for deriving from the output of said counter an al-ternate address information signal corresponding to the selection signal, means responsive to the alternate address information signal for placing said data into the sequentially correct stage of the shift register corresponding to the storage address defined by the encoded input signal as said register is being shifted by said interrogating means for sequential read-out of each storage address.

Claim 3

The system of claim 1 wherein said memory has a metal-oxide-semiconductor construction.

Claim 4

A selection and memory system for selectively retrieving data respectively stored at different storage addresses of a memory formed by a plurality of shift registers, said system comprising: means for writing data in said memory at an address corresponding to an encoded selection input signal, said means having a first portion for storing address information defining one of said plurality of memory shift registers and a second portion for storing address information defining a stage of said one shift register; interrogating means for sequentially interrogating the storage addresses of said memory by successively shifting the shift registers thereof; a first counter for continuously storing the shifted register status and providing an output indicative thereof; a second counter for storing an identifying count indicative of the register being shifted for interrogation of the memory and providing an output indicative thereof; means for comparing the output identifying indication of said second counter with the address information in said first portion of said storage means to provide a predetermined gating signal when the encoded input signal corresponds to a storage address of the register being shifted; means for adding the output of said first counter to the contents of said second portion of said storage means; and logic means coupling the output of said adding means to the memory shift registers for placing said data into the sequentially correct stage of the register being shifted, corresponding to the storage address defined by the encoded iNput signal, in response to said predetermined gating signal.

Claim 5

A selection and memory system for selectively retrieving data respectively stored at different storage addresses of a memory formed by a plurality of shift registers, said system comprising: means for writing data in said memory at an address corresponding to an encoded selection input signal, said means having a first portion for storing address information defining one of said plurality of memory shift registers and a second portion for storing address information defining a stage of said one shift register; interrogating means for sequentially interrogating the storage addresses of said memory by successively shifting the shift registers thereof; a first counter for continuously storing the shifted register status and providing an output indicative thereof; a second counter for storing an identifying count indicative of the register being shifted for interrogation of the memory and providing an output indicative thereof; means for comparing the output identifying indication of said second counter with the address information in said first portion of said storage means to provide a predetermined gating signal when the encoded input signal corresponds to a storage address of the register being shifted; means for adding the output of said first counter to the contents of said second portion of said storage means; and logic means coupling the output of said adding means to the memory shift registers for placing said data into the sequentially correct stage of the register being shifted, corresponding to the storage address defined by the encoded iNput signal, in response to said predetermined gating signal.

Claim 6

In an automatic phonograph, a selection and memory system for selecting and storing the selection information for each record to be played, each record being stored in a different predetermined storage location, said system comprising, information input means for providing a selectable encoded signal corresponding to a given record in a predetermined storage location, a shift register memory having storage addresses cor-responding to the respective predetermined storage locations of said records, buffer storage means responsive to the encoded selec-tion signal for storing an address information signal defining a stage of a shift register of said memory corresponding to the selection signal, means responsive to the address information signal in said buffer storage means for writing a retrieval command signal into said shift register memory at an address corresponding to said encoded selection signal, interrogating means for sequentially reading out the storage addresses of said memory by successively shifting a shift register thereof, a counter for storing the status of said shift register, means for adding the output of said counter to said address information signal to provide an alternate address information signal corresponding to the selection signal, and means responsive to the alternate address information signal for placing said retrieval command signal into a sequentially correct stage of the shift register corresponding to the storage address defined by the encoded selection signal as said register is being shifted by said interrogating means for sequential read-out of each storage address.

Claim 7

In an automatic phonograph, a selection and memory system for selecting and storing the selection information for each record to be played, each record being stored in a different predetermined storage location, said system comprising, information input means for providing a selectable encoded signal corresponding to a given record in a predetermined storage location, a shift register memory having storage addresses cor-responding to the respective predetermined storage locations of said records, buffer storage means responsive to the encoded selec-tion signal for storing an address information signal defining a stage of a shift register of said memory corresponding to the selection signal, means responsive to the address information signal in said buffer storage means for writing a retrieval command signal into said shift register memory at an address corresponding to said encoded selection signal, interrogating means for sequentially reading out the storage addresses of said memory by successively shifting a shift register thereof, a counter for storing the status of said shift register, means for adding the output of said counter to said address information signal to provide an alternate address information signal corresponding to the selection signal, and means responsive to the alternate address information signal for placing said retrieval command signal into a sequentially correct stage of the shift register corresponding to the storage address defined by the encoded selection signal as said register is being shifted by said interrogating means for sequential read-out of each storage address.

Claim 8

The system of claim 4 for use with a phonograph having a multiple speed turntable, wherein said memory comprises a plurality of shift registers, a further counter for storing an identifying count indicative of the particular shift register being shifted for interrogation of the memory, and means responsive to said further counter for providing a signal defining one or another of said multiple speeds in accordance with a predetermined arrangement for each state of said further counter.