US3972024A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable microprocessor
Assignee: Unisys Corp
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Filing: 1974-03-27
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Granted: 1976-07-27
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Expires: 1994-03-27
Abstract
Abstract An improved microinstruction memory addressing method and apparatus within a serial-bit microinstruction processor incorporating internal, serial-byte transfer, is provided by addition to and alteration of memory control circuitry wherein the resulting permissible microinstruction set for controlling the processor may be expanded to include a CALL, GO-TO and EXECUTE operations, thus increasing the programmatic capabilities in the processor. The micro-code needed to define more complicated program operations, and thus the time used to perform these operations, may therefore be greatly reduced. Changes may also be made in existing timing circuitry.
Inventors
- 👤 Franklin T. Schroeder
- 👤 John P. McAllister
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:33
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
141 words
In a microprocessing apparatus for cyclically processing microinstructions addressably stored in a microprogram memory means, certain ones of said microinstructions including address bits, the improvement comprising: an incrementable first register for storing address bits to addressably select microinstructions for retrieval from said microprogram memory means; a second register for storing address bits loadable into said first register; means, responsive to address bits stored in said first register and operative during a single process cycle, for retrieving from said microprogram memory means a selected one of said certain ones of said microinstructions and loading the address bits included therein into said second register; means for incrementing within said single process cycle the contents of said first register; and means for swapping within said single process cycle said incremented contents of said first register and said loaded address bits in said second register.
Claim 2
Dependent Claim
141 words
In a microprocessing apparatus for cyclically processing microinstructions addressably stored in a microprogram memory means, certain ones of said microinstructions including address bits, the improvement comprising: an incrementable first register for storing address bits to addressably select microinstructions for retrieval from said microprogram memory means; a second register for storing address bits loadable into said first register; means, responsive to address bits stored in said first register and operative during a single process cycle, for retrieving from said microprogram memory means a selected one of said certain ones of said microinstructions and loading the address bits included therein into said second register; means for incrementing within said single process cycle the contents of said first register; and means for swapping within said single process cycle said incremented contents of said first register and said loaded address bits in said second register.
Claim 3
Dependent Claim
163 words
In a microprocessing apparatus for cyclically processing microinstructions addressably stored in a microprogram memory means, certain ones of said microinstructions including address bits, the improvement comprising: an incrementable first register for storing address bits to addressably select microinstructions for retrieval from said microprogram memory means; a second register for storing address bits loadable into said first register; first means, responsive to address bits stored in said first register and operative during a single process cycle, for retrieving from said microprogram memory means a selected one of said certain ones of said microinstructions and loading the address bits included therein into said second register; second means, concurrently operative with said first means, for transferring to said first register the address bits stored in said second register immediately preceding the loading thereof by said first means; and third means, operative within said single cycle following the operations of said first and said second means, for swapping the contents of said first and said second registers.
Claim 4
Dependent Claim
163 words
In a microprocessing apparatus for cyclically processing microinstructions addressably stored in a microprogram memory means, certain ones of said microinstructions including address bits, the improvement comprising: an incrementable first register for storing address bits to addressably select microinstructions for retrieval from said microprogram memory means; a second register for storing address bits loadable into said first register; first means, responsive to address bits stored in said first register and operative during a single process cycle, for retrieving from said microprogram memory means a selected one of said certain ones of said microinstructions and loading the address bits included therein into said second register; second means, concurrently operative with said first means, for transferring to said first register the address bits stored in said second register immediately preceding the loading thereof by said first means; and third means, operative within said single cycle following the operations of said first and said second means, for swapping the contents of said first and said second registers.
Claim 5
Dependent Claim
125 words
In a microprocessing apparatus for cyclically processing microinstructions addressably stored in a microprogram memory means, certain ones of said microinstructions including address bits, the improvement comprising: an incrementable first register for storing address bits to addressably select microinstructions for retrieval from said microprogram memory means; a second register for storing address bits loadable into said first register; first activatable means for incrementing said first register; second activatable means for swapping the contents of said first and second registers; third activatable means for executing the microprogram memory means microinstruction selected by the address bits stored in said first register; and means for activating sequentially within two process cycles said first means, said second means, said third means, and again said first means, and said second means.
Claim 6
Dependent Claim
125 words
In a microprocessing apparatus for cyclically processing microinstructions addressably stored in a microprogram memory means, certain ones of said microinstructions including address bits, the improvement comprising: an incrementable first register for storing address bits to addressably select microinstructions for retrieval from said microprogram memory means; a second register for storing address bits loadable into said first register; first activatable means for incrementing said first register; second activatable means for swapping the contents of said first and second registers; third activatable means for executing the microprogram memory means microinstruction selected by the address bits stored in said first register; and means for activating sequentially within two process cycles said first means, said second means, said third means, and again said first means, and said second means.
Claim 7
Dependent Claim
144 words
In a microprocessing apparatus for cyclically processing microinstructions addressably stored in a microprogram memory means, certain ones of said microinstructions requiring a relatively short process cycle for implementation, each of said certain ones including coded identifying information, the improvement comprising: means for generating a periodic process cycle for sequencing the cyclical processing of said microinstructions, the process cycle being sufficient in duration for processing each microinstruction stored in said microprogram memory means; activatable short cycle means interacting with said generating means for producing a relatively short process cycle, said relatively short process cycle being sufficient in duration for the processing of each of said certain ones of said microinstructions; and means for decoding said identifying information of each of said certain ones of said microinstructions immediately preceding the processing thereof and for activating said short cycle means upon said decoding of said identifying information.
Claim 8
Dependent Claim
144 words
In a microprocessing apparatus for cyclically processing microinstructions addressably stored in a microprogram memory means, certain ones of said microinstructions requiring a relatively short process cycle for implementation, each of said certain ones including coded identifying information, the improvement comprising: means for generating a periodic process cycle for sequencing the cyclical processing of said microinstructions, the process cycle being sufficient in duration for processing each microinstruction stored in said microprogram memory means; activatable short cycle means interacting with said generating means for producing a relatively short process cycle, said relatively short process cycle being sufficient in duration for the processing of each of said certain ones of said microinstructions; and means for decoding said identifying information of each of said certain ones of said microinstructions immediately preceding the processing thereof and for activating said short cycle means upon said decoding of said identifying information.
Claim 9
Dependent Claim
15 words
The apparatus of claim 4 wherein said relatively short process cycle is presettable in duration.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-27 | 1980-01-26 | 1980-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-27 | 1984-01-26 | 1984-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-27 | 1988-01-26 | 1988-07-27 | $7700.00 | Window Closed / Lapsed |