Micro-program control system

Claim 1

A micro-program control system for electronic computing apparatus for effecting data processing in time-shared fashion in accordance with a preselected number of micro-programs comprising: a memory having at least said preselected number of microprograms stored therein, an address register, timing means for cyclically controlling said apparatus for said plural micro-programs, a plurality of output registers controlled by said timing means for storing micro-instructions for said respective microprograms, read out from said memory at the memory addresses cyclically identified by the contents of said address register, first address updating means for providing a first next instruction address based on the memory address identified by the current contents of said address register, a plurality of additional registers for said respective microprograms, gate means controlled by said timing means for loading said additional registers with the first next instruction addresses for said respective micro-programs, second address updating means for selectively providing in response to a micro-instruction stored in each of said output registers, a second next instruction address based on one of the prior processed micro-instructions and the instruction obtained as a result of previous data processing, and control gating means controlled by said timing means and a logical combination of the prior-processed micro-instruction and the result of data processing effected in accordance therewith for loading said address register with either of said first next instruction address and the selected second next instruction address.

Claim 12

A method for effecting micro-program control of electronic computing apparatus which includes a memory, an address register, an address updating circuit, plural arithmetic circuits and timing circuitry for cyclically subdividing the control of said computing apparatus into a plurality of clock phases depending upon the number of micro-programs to be simultaneously executed on a time shared basis, comprising the steps of reading out a micro-program instruction for a first one of said micro-programs being executed during each clock phase, effecting execution during that clock phase of an instruction for a second micro-program read from the memory during a preceding clock phase, and impressing a next address for a third one of the micro-programs in said address register during that clock phase, said address representing a selection between a sequential updating of the previous address for said third micro-program and a transfer for said third micro-program, said memory thereby being interrogated to read out a new micro-instruction during each clock phase.

Claim 13

A method for effecting micro-program control of electronic computing apparatus which includes a memory, an address register, an address updating circuit, plural arithmetic circuits and timing circuitry for cyclically subdividing the control of said computing apparatus into a plurality of clock phases depending upon the number of micro-programs to be simultaneously executed on a time shared basis, comprising the steps of reading out a micro-program instruction for a first one of said micro-programs being executed during each clock phase, effecting execution during that clock phase of an instruction for a second micro-program read from the memory during a preceding clock phase, and impressing a next address for a third one of the micro-programs in said address register during that clock phase, said address representing a selection between a sequential updating of the previous address for said third micro-program and a transfer for said third micro-program, said memory thereby being interrogated to read out a new micro-instruction during each clock phase.