Patent US3900746A successfully refreshed from Google Patents.
US3900746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage level conversion circuit
Assignee: International Business Machines Corp
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Filing: 1974-05-03
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Granted: 1975-08-19
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Expires: 1994-05-03
Abstract
Abstract An interface circuit utilizing bipolar and complementary field effect transistors for interfacing low voltage circuits with higher voltage circuits. The circuit input at the lower voltage level comprises a bipolar transistor connected as an emitter follower. The circuit output is a FET inverter having its input connected to the collector of the bipolar transistor. A divertable current sink in the form of a third FET is connected in series with the inverter and to the emitter of the bipolar transistor.
Inventors
- 👤 Wayne R Kraft
- 👤 Robert P Lowden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:10
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
214 words
A voltage level translating circuit providing at its output terminal a signal having a voltage level within a first predetermined range in response to a signal at its input terminal having a voltage level within a second predetermined range comprising: first and second reference potentials; a bipolar transistor, said input signal being applied to the base of said bipolar transistor; a complementary field effect transistor inverter means including a first field effect transistor of a first channel type and a second field effect transistor of a second channel type complementary to said first channel type; said complementary field effect transistor inverter means connected to said first reference potential for generating said output signal, the gate electrodes of the complementary field effect transistors of said inverter means being connected to the collector of said bipolar transistor; resistance means connected between the collector of said bipolar transistor and said first reference potential; and variable current sink means connected to the emitter of said bipolar transistor and to said inverter means and being responsive to the voltage level at the collector of said bipolar transistor for holding said output terminal at said second reference potential when the bipolar transistor is nonconductive and for operating said bipolar transistor in the emitter-follower mode when said bipolar transistor is conductive.
Claim 2
Dependent Claim
214 words
A voltage level translating circuit providing at its output terminal a signal having a voltage level within a first predetermined range in response to a signal at its input terminal having a voltage level within a second predetermined range comprising: first and second reference potentials; a bipolar transistor, said input signal being applied to the base of said bipolar transistor; a complementary field effect transistor inverter means including a first field effect transistor of a first channel type and a second field effect transistor of a second channel type complementary to said first channel type; said complementary field effect transistor inverter means connected to said first reference potential for generating said output signal, the gate electrodes of the complementary field effect transistors of said inverter means being connected to the collector of said bipolar transistor; resistance means connected between the collector of said bipolar transistor and said first reference potential; and variable current sink means connected to the emitter of said bipolar transistor and to said inverter means and being responsive to the voltage level at the collector of said bipolar transistor for holding said output terminal at said second reference potential when the bipolar transistor is nonconductive and for operating said bipolar transistor in the emitter-follower mode when said bipolar transistor is conductive.
Claim 3
Dependent Claim
27 words
A voltage level translating circuit as in claim 1 wherein said current sink means is a third field effect transistor connected in series with said inverter means.
Claim 4
Dependent Claim
53 words
A voltage level translating circuit as in claim 2 wherein the transconductance of said third field effect transistor and the field effect transistor of said complementary inverter which is of the same channel type as said third transistor is larger than the transconductance of the other field effect transistor in said complementary inverter.
Claim 5
Dependent Claim
18 words
A voltage level translating circuit as in claim 1 wherein said resistance means is an active load device.
Claim 6
Dependent Claim
32 words
A voltage level translating circuit as in claim 4 wherein said active load device comprises a third field effect transistor having a gate electrode connected to the base of said bipolar transistor.
Claim 7
Dependent Claim
150 words
A voltage level translating circuit providing at its output terminal a signal having a voltage level within a first predetermined range in response to a signal at its input terminal having a voltage level within a second predetermined range comprising: a first field effect transistor, a bipolar transistor and a second effect field effect transistor of opposite channel type to said first field effect transistor connected in series relationship between first and second reference potentials, said input signal being applied to the base of said bipolar transistor and the gate of said first field effect transistor; inverter means comprising complementary field effect transistors for generating said output signal, and connected in series relationship with said second field effect transistor between said first and second reference potentials; the gate electrodes of the complementary field effect transistors and said second field effect transistor being connected to the collector of said bipolar transistor.
Claim 8
Dependent Claim
150 words
A voltage level translating circuit providing at its output terminal a signal having a voltage level within a first predetermined range in response to a signal at its input terminal having a voltage level within a second predetermined range comprising: a first field effect transistor, a bipolar transistor and a second effect field effect transistor of opposite channel type to said first field effect transistor connected in series relationship between first and second reference potentials, said input signal being applied to the base of said bipolar transistor and the gate of said first field effect transistor; inverter means comprising complementary field effect transistors for generating said output signal, and connected in series relationship with said second field effect transistor between said first and second reference potentials; the gate electrodes of the complementary field effect transistors and said second field effect transistor being connected to the collector of said bipolar transistor.
Claim 9
Dependent Claim
189 words
A voltage level translating circuit providing at its output terminal a signal having a voltage level within a first predetermined range in response to a signal at its input terminal having a voltage level within a second predetermined range comprising: first, second and third reference potentials, the magnitude of said first reference potential being greater than that of said third reference potential; a bipolar transistor, said input signal being applied to its base; inverter means comprising complementary field effect transistors and connected to said first reference potential for generating said output signal, the gate electrodes of the complementary field effect transistors being connected to the collector of said bipolar transistor; resistance means connected between the collector of said bipolar transistor and said third reference potential; and variable current sink means connected to the emitter of said bipolar transistor and to said inverter means and being responsive to the voltage level at the collector of said bipolar transistor for holding said output terminal at said second reference potential when the bipolar transistor is non-conductive and for operating said bipolar transistor in the emitter-follower mode when said bipolar transistor is conductive.
Claim 10
Dependent Claim
189 words
A voltage level translating circuit providing at its output terminal a signal having a voltage level within a first predetermined range in response to a signal at its input terminal having a voltage level within a second predetermined range comprising: first, second and third reference potentials, the magnitude of said first reference potential being greater than that of said third reference potential; a bipolar transistor, said input signal being applied to its base; inverter means comprising complementary field effect transistors and connected to said first reference potential for generating said output signal, the gate electrodes of the complementary field effect transistors being connected to the collector of said bipolar transistor; resistance means connected between the collector of said bipolar transistor and said third reference potential; and variable current sink means connected to the emitter of said bipolar transistor and to said inverter means and being responsive to the voltage level at the collector of said bipolar transistor for holding said output terminal at said second reference potential when the bipolar transistor is non-conductive and for operating said bipolar transistor in the emitter-follower mode when said bipolar transistor is conductive.
Claim 11
Dependent Claim
139 words
An interface circuit comprising: first, second and third means for supplying reference potentials; a bipolar transistor with its base as the input of said interface circuit; a complementary field effect transistor inverter including a first field effect transistor and a second field effect transistor of a channel type complementary to that of said first field effect transistor and providing the output of said interface circuit; a third field effect transistor connected in series with said inverter between said first and second reference potential supplying means; the gate electrodes of said first, second and third field effect transistors being connected to the collector of said bipolar transistor; the emitter of said bipolar transistor being connected to the common terminal of said inverter and said third transistor; and resistance means connected between said collector and said third reference potential supplying means.
Claim 12
Dependent Claim
139 words
An interface circuit comprising: first, second and third means for supplying reference potentials; a bipolar transistor with its base as the input of said interface circuit; a complementary field effect transistor inverter including a first field effect transistor and a second field effect transistor of a channel type complementary to that of said first field effect transistor and providing the output of said interface circuit; a third field effect transistor connected in series with said inverter between said first and second reference potential supplying means; the gate electrodes of said first, second and third field effect transistors being connected to the collector of said bipolar transistor; the emitter of said bipolar transistor being connected to the common terminal of said inverter and said third transistor; and resistance means connected between said collector and said third reference potential supplying means.
Claim 13
Dependent Claim
21 words
An interface circuit as in claim 8 wherein said first and third means for supplying a reference potential are commonly connected.
Claim 14
Dependent Claim
40 words
An interface circuit as in claim 9 wherein said active load device comprises a fourth field effect transistor of opposite channel type to said third field effect transistor having a gate electrode connected to the base of said bipolar transistor.
Claim 15
Dependent Claim
16 words
An interface circuit as in claim 8 wherein said resistance means is an active load device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-18 | 1979-02-17 | 1979-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-18 | 1983-02-17 | 1983-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-18 | 1987-02-17 | 1987-08-19 | $7700.00 | Window Closed / Lapsed |