Pulses of the same or an opposite polarity to electrodes of a plasma display panel

Claim 2

A circuit for driving an external electrode discharge display panel having a plurality of gas discharge cells, a first and a second group of electrodes disposed on opposite sides of said cells, and means for cyclically supplying a first pulse train of a predetermined duration to the electrodes of said first group, wherein the improvement comprises means for supplying a second pulse train to each electrode of said second group, said second pulse train supplying means comprising means for supplying pulses of a polarity opposite to the pulses of said first pulse train and substantially coincident with said first pulse train when the display discharge cell associated with the first and second group electrodes respectively receiving said first and second pulse trains is to glow, and means for otherwise supplying pulses of the same polarity as the pulses of said first pulse train wherein said first and second pulse train supplying means supply a direct-current voltage component to the cells while said first pulse train is not supplied to the electrodes of said first pulse train is not supplied to the electrodes of said first electrode group disposed on one side of said cells.

Claim 3

A combination as in claim 1, wherein said discharge cells are characterized by a firing potential Vf and a glow abating potential Vs, and whereins aid first and second pulse train supplying means supply pulses of a voltage amplitude V1 and V2, where Vf, Vs, V1 and V2 are real numbers wherein 2(Vf+Vs) about V1 about V2 about Vf-Vs.

Claim 4

A circuit for driving an external electrode discharge display panel having a plurality of gas discharge cells, a first and a second group of electrodes disposed on opposite sides of said cells, and means for cyclically supplying a first pulse train of a predetermined duration to the electrodes of said first group, wherein the improvement comprises means for supplying a second pulse train to each electrode of said second group , said second pulse train supplying means comprising means for supplying pulses of a polarity oppostie to the pulse traiin the display dishcarge cell associated with the first and second group electrodes respectively receiving said first and second pulse trains is to glow, and means for otherwise supplying pulses of the same polarity as the pulses of said first pulse train further comprising a clock generator for supplying clock pulses to said first and second pulse train supplying means, respectively, wherein said second pulse train supplying means comprises an inverter for inverting said clock pulses, first AND gates supplied with said clock pulses and said second control signals, control signal inverters for inverting said second control signals, second AND gates supplied with the inverted clock pulses and the respective inverted second control signals, and NOR gates responsive to the output signals of said first AND gates and the corresponding second ANd gates for producing said second pulse trains.

Claim 5

A circuit for driving an external electrode discharge display panel having a plurality of gas discharge cells, a first and a second group of electrodes disposed on opposite sides of said cells, and means for cyclically supplying a first pulse train of a predetermined duration to the electrodes of said first group, wherein the improvement comprises means for supplying a second pulse train to each electrode of said second group , said second pulse train supplying means comprising means for supplying pulses of a polarity oppostie to the pulse traiin the display dishcarge cell associated with the first and second group electrodes respectively receiving said first and second pulse trains is to glow, and means for otherwise supplying pulses of the same polarity as the pulses of said first pulse train further comprising a clock generator for supplying clock pulses to said first and second pulse train supplying means, respectively, wherein said second pulse train supplying means comprises an inverter for inverting said clock pulses, first AND gates supplied with said clock pulses and said second control signals, control signal inverters for inverting said second control signals, second AND gates supplied with the inverted clock pulses and the respective inverted second control signals, and NOR gates responsive to the output signals of said first AND gates and the corresponding second ANd gates for producing said second pulse trains.