Driving circuit for a plasma display panel comprising pnp and npn transistors

Claim 1

A circuit arrangement for making electric power source means and control signal generating means cooperate to drive a plasma display panel including a coplanar array of plasma discharge cells, a plurality of first electrodes, and a plurality of second electrodes, said first and second electrodes being disposed on both sides of said array at the outside of said cells, wherein the improvement comprises a plurality of PNP transistors coupled to the respective ones of said first electrodes and a like number of NPN transistors coupled to the respective ones of said second electrodes, said PNP and NPN transistors being further coupled to said power source means and said control signal generating means and cooperatively producing a high frequency voltage to apply said voltage to a pair of the electrodes selected one each from said first and second electrodes in response to control signals generated by said control signal generating means, said power source means including a first and a second conductor between which a D.C. power is developed, each of said PNP and NPN transistors including an emitter, a collector, and a base electrode, wherein said control signal generating means comprises high frequency pulse generating means and address pulse generating means, the emitter electrodes of said PNP transistors are connected direct to said first conductor, the collector electrodes of said PNP transistors are connected to the respective ones of said first electrodes directly and to said second conductor through resistors, respectively, the emitter electrodes of said NPN transistors are connected direct to said second conductors, the collector electrodes of said NPN transistors are connected to the respective ones of said second electrodes directly and to said first conductor through resistors, respectively, and the base electrodes of said PNP and NPN transistors are coupled to said high frequency pulse generating means and said address pulse generating means whereby one of said PNP transistors and one of said NPN transistors selected by an address pulse generated by said address pulse generating means cooperatively amplify high frequency pulses generated by said high frequency pulse generating means to deliver the amplified high frequency pulses to a pair of the electrodes connected direct to the collector electrodes of the selected PNP and NPN transistors, wherein: said high frequency pulse generating means comprises first and second high frequency pulse generating means for successively simultaneously producing first and second high frequency pulses, respectively, said address pulse generating means comprises first and second address pulse generating means for successively simultaneously producing first and second address pulses, respectively, and said arrangement further comprises AND circuits, each comprising a first input terminal, a second input terminal, and an output terminal, the output terminals being coupled to the respective base electrodes of said PNP and NPN transistors, the first input terminals of the AND circuits coupled to said PNP and NPN transistors being connected to said first and second high frequency pulse generating means to be simultaneously supplied with said first and second high frequency pulses, respectively, the second input terminals of the AND circuits coupled to said PNP and NPN transistors being connected to said first and second address pulse generating means to be selectively supplied with said first and second address pulses, respectively.