US3727102A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selection and addressing circuitry for matrix type gas display panel
Assignee: OI Glass Inc
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Filing: 1970-08-03
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Granted: 1973-04-10
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Expires: 1990-08-03
Abstract
Abstract There is disclosed a collection and addressing diode-resistor logic matrix for row column conductor arrays in a gas discharge display and memory panel wherein the alternating sustaining currents from the panel are caused to bypass the logic circuits in returning to the sustaining signal source by a diode for each conductor in the row-column conductor array.
Inventors
- 👤 W Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:16
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/22; G09G3/28; G09G3/288; G09G3/296; G09G3/297
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
159 words
In a gas discharge panel having a plurality of dielectrically coated parallel row conductors and a plurality of dielectrically coated column conductors for carrying discharge condition manipulating voltage pulses and alternating sustaining potentials to selected row-column conductor cross-points, and a dioderesistor logic matrix in which each junction between the connected ends of a diode and a resistor in the logic matrix is connected to one of said conductors, respectively, and the coincidence of a selectively applied voltage pulse on the resitor end from a resistor pulse source and a a selectively applied control signal on the end from a diode central signal source, opposite each said junction, respectively, is effective to cause the voltage pulse on said resistor to appear on the conductor connected to said junction, the improvement comprising, non linear circuit means for bypassing the alternating sustaining potential around the diode-resistor elements in said logic matrix for a portion of the cycle of said alternating sustaining potential.
Claim 2
Dependent Claim
159 words
In a gas discharge panel having a plurality of dielectrically coated parallel row conductors and a plurality of dielectrically coated column conductors for carrying discharge condition manipulating voltage pulses and alternating sustaining potentials to selected row-column conductor cross-points, and a dioderesistor logic matrix in which each junction between the connected ends of a diode and a resistor in the logic matrix is connected to one of said conductors, respectively, and the coincidence of a selectively applied voltage pulse on the resitor end from a resistor pulse source and a a selectively applied control signal on the end from a diode central signal source, opposite each said junction, respectively, is effective to cause the voltage pulse on said resistor to appear on the conductor connected to said junction, the improvement comprising, non linear circuit means for bypassing the alternating sustaining potential around the diode-resistor elements in said logic matrix for a portion of the cycle of said alternating sustaining potential.
Claim 3
Dependent Claim
58 words
The invention defined in claim 1 wherein said nonlinear circuit element is a diode, there being at least one diode connected to each panel row and column conductor and having the like electrode thereof commonly connected to each for the rod and column conductor, respectively, and means connecting said common connection to the source of said sustainer potential.
Claim 4
Dependent Claim
114 words
The invention defined in claim 1 wherein there are a plurality of said resistor pulse sources individually connected to selected ones of resistors in said matrix and a plurality of diode logic pulse sources connected to selected individual logic diode elements, said resistor pulse sources and said diode logic element pulse sources being connected in a logic pattern to said resistors and said diodes, whereby the coincidence of pulses at selected diode-resistor common junction is effective to supply a discharge condition manipulating voltage pulSe to the conductor connected thereto without applying a pulse potential to conductors which may be connected to diode-resistor logic elements having common junctions connected to unselected conductors on the panel.
References Cited (Backward Citations)
US3499167A
Cited
US3513327A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-09 | 1976-10-09 | 1977-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-09 | 1980-10-09 | 1981-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-09 | 1984-10-09 | 1985-04-10 | $7700.00 | Window Closed / Lapsed |