US3614739A
Expired / Lapsed
US
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Integrated driving circuitry for gas discharge panel
Assignee: OI Glass Inc
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Filing: 1969-05-02
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Granted: 1971-10-19
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Expires: 1989-05-02
Abstract
Abstract Solid-state low-level to high-level interfacing circuits for multiple discharge gas discharge devices capable of feeding through a high-level periodic sustaining voltage to the discharge device with minimum degradation. The output is the algebraic sum of the periodic sustaining voltage and a level converted logic signal. NPN circuits are used to drive one set of conductors in an array and PNP circuits are used for driving transversely related conductor arrays in the gas discharge device. Dielectric isolation in the fabrication of the integrated circuits is utilized and the circuits are such as to not require any inductance or capacitance elements, thus reducing cost and size of the circuits. The circuit appears as a low impedance to the load. There is no mixing of active elements (NPN vs PNP) in a circuit wafer or chip. Consult the specification for features and details.
Inventors
- 👤 William E Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:28
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; G; G09; G09G; G09G3/00; G09G3/20; G09G3/22; G09G3/28; G09G3/288; G09G3/296; G09G3/297; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
52 words
The invention defined in claim 1 wherein each said circuit configuration includes diode means formed in each said monolithic body and connected between sAid final contact area and a point in said circuit which is common to the base of said normally ON transistor and the collector of said normally OFF transistor.
Claim 2
Dependent Claim
48 words
The invention defined in claim 1 wherein a resistive circuit component in each said circuit configuration is connected between the collector of said normally ON transistor and a point which is common to the base of said normally ON transistor and the collector of said normally OFF transistor.
Claim 3
Dependent Claim
48 words
The invention defined in claim 2 wherein a resistive circuit component in each said circuit configuration is connected between the collector of said normally ON transistor and said point which is common to the base of said normally ON transistor and the collector of said normally OFF transistor.
Claim 4
Dependent Claim
28 words
The invention defined in claim 1 wherein the transistor circuit components in each said monolithic semiconductor body are formed in dielectrically isolated device islands in the semiconductor body.
Claim 5
Dependent Claim
27 words
The invention defined in claim 4 wherein the transistors and diode means of said circuit configuration are formed in dielectrically isolated device islands in the semiconductor body.
Claim 6
Dependent Claim
33 words
The invention defined in claim 4 wherein each said circuit configuration includes further diode means for speeding the switching response of said transistors to a low-level input pulse voltage on said input terminal.
Claim 7
Dependent Claim
64 words
The invention defined in claim 7 wherein a resistive voltage divider is in each said circuit configuration is connected at one end to said low-level pulse voltage input terminal, at the intermediate point to the base electrode of said normally OFF transistor and at the opposite end to one of said pair of control areas for applying a high-level periodic voltage to said circuit.
Claim 8
Dependent Claim
233 words
An integrated circuit element for supplying sustaining voltages and discharge manipulating pulse voltages to one conductor in a gas discharge device in which transversely oriented conductor effecting discharges in the gas have dielectric charge-storage means for charges produced on discharge interposed between said conductors and the gas, comprising, a monolithic semiconductor body processed to include a plurality of resistive and transistor circuit components connected by conductors in the circuit configuration described hereinafter including a plurality of contact areas through which connections to said circuit configuration are made, said circuit configuration including a pair of like conductivity type transistor switches connected such that one of said transistor switches is normally ON and the other of said transistor switches is normally OFF and to reverse the conductive states of said transistor switches, one of said contact areas comprising a low-level pulse voltage input terminal connected to the base of said normally OFF transistor to render said normally OFF transistor ON and said normally ON transistor OFF, on appearance of a low-level pulse voltage on said one contact area, a pair of said contact areas for applying a high-level periodic voltage to the collector of said normally OFF transistor, respectively, and a high-level unidirectional voltage to the emitter of said normally off transistor, and a final contact area constituting the output terminal from said integrated circuit said final contact area being connected to said one conductor.
Claim 9
Dependent Claim
30 words
An integrated circuit element as defined in claim 9 wherein the transistor circuit components in said monolithic semiconductor body are formed in dielectrically isolated device islands in the semiconductor body.
Claim 10
Dependent Claim
281 words
A circuit for converting a low-level pulse voltage to a high-level pulse voltage and algebraically combining said high-level pulse voltage with a high-level periodic voltage comprising, in combination, a pair of input terminals for connection to a low-impedance high-voltage level direct current voltage source, an output terminal, a normally nonconductive first transistor, means connecting the emiTter of said first transistor to one input terminal of said high-voltage level current voltage source, diode means connecting the collector of said first transistor to said output terminal, a resistance element connecting the other input terminal of said high-level direct current source to the collector of said first transistor, means for applying said low-level pulse voltage to said first transistor to render said first transistor conductive and apply the high-voltage level direct current voltage from said source to said output terminal through said diode means, a normally conductive second transistor, means connecting the emitter of said second transistor to said output terminal, means connecting the collector to said second transistor to the other input terminal for said high-voltage level direct current voltage source, means connecting the base of said second transistor to the emitter of said first transistor whereby said normally conductive second transistor is rendered nonconductive on said first transistor being rendered conductive voltage to the base thereof, a source of high-level periodic voltage, and means for applying said high-level periodic voltage to the collector of said second transistor, whereby said high-level periodic voltage is applied to said output terminal through said second transistor during the conduction times thereof and to said output terminal through said low-impedance high-voltage level direct current voltage source and said first transistor during conduction times of said first transistor.
Claim 11
Dependent Claim
22 words
The invention defined in claim 11 wherein said circuit is one of a plurality of similar circuits on an integrated circuit chip.
Claim 12
Dependent Claim
27 words
The invention defined in claim 12 wherein said integrated circuit chip contains a plurality of device islands dielectrically isolated from each other and in a common matrix.
Claim 13
Dependent Claim
35 words
The invention defined in claim 13 wherein each normally conductive second transistor of each circuit is in its own device island and all of said normally nonconductive first transistors are in a common device island.
Claim 14
Dependent Claim
189 words
An interface system for coupling low-voltage level information signals from an information source to traversely oriented insulated conductor arrays in a gas discharge display panel requiring oppositely phased high-voltage level pulse information signals and oppositely phased periodic sustaining voltages applied to and transversely oriented conductors for displaying the information comprising, in combination, first integrated circuit means for translating low-voltage level information signals from said source to unidirectional high-voltage information signals and applying same to conductors of one conductor array, and second integrated circuit means for translating low-voltage level information signals from said source to unidirectional, high-voltage level information signals and applying same to conductors of the conductor array transversely oriented with respect to said one conductor array, a generator for generating a pair of oppositely phased periodic voltages, means for applying one phase of said pair of periodic voltages to said first integrated circuit means and the other phase of said pair to said second integrated circuit means, each said integrated circuit means algebraically adding one of said oppositely phased unidirectional high-voltage levels produced thereby to the periodic voltage applied thereto, respectively, to thereby display information on said panel.
Claim 15
Dependent Claim
67 words
The invention defined in claim 15 including a generator for generating a pair of oppositely phased periodic voltages, means for applying one phase of said pair of periodic voltages to said first integrated circuit means and the other phase of said pair to said second integrated circuit means, each said integrated circuit means algebraically adding unidirectional high-voltage levels produced thereby to the periodic voltage applied thereto, respectively.
Claim 16
Independent Claim
457 words
A system For driving a multiple discharge gas discharge device wherein a pair of transversely oriented conductor arrays are dielectrically isolated from a thin gas discharge medium between said pair of conductor arrays comprising, in combination, at least a first monolithic semiconductor body processed to provide a plurality of first resistive and transistor circuit components connected by conductors to form a plurality of identical but electrically isolated switching circuits having the circuit configuration described hereinafter, including a plurality of contact areas through which connections to said circuit configuration are made, at least a second monolithic semiconductor body processed to provide a plurality of second resistive and transistor circuit components connected by conductors to form a second plurality of identical but electrically isolated switching circuits having the circuit configuration described hereinafter, including a plurality of contact areas through which connections to said circuit configuration are made, each said circuit configuration including, a pair of transistor switches connected such that one of said transistor switches is normally ON and the other said transistor switches is normally OFF, one of said contact areas comprising a low-level pulse voltage input terminal connected to the base of said normally OFF transistor to render said normally OFF transistor ON and said normally ON transistor OFF on appearance of a low-level pulse voltage at said one contact area, a pair of said contact for applying a high-level periodic voltage to the collector of said normally ON transistor and to the emitter of said normally OFF transistor, and a high-level unidirectional voltage to the emitter of said normally OFF transistor, and, a final contact area constituting the output terminal from said circuit configuration, means individually connecting each final contact area of said first circuit configuration on said first monolithic body to conductors in a first of said conductor arrays, respectively, means individually connecting each final contact area of said second circuit configurations on said second monolithic body to conductors in the second of said conductor arrays, respectively, a first source of high-level periodic voltage and means commonly connecting said first source of high-level periodic voltage to all of said pairs of contact areas on said first monolithic semiconductor body, a second source of high-level periodic voltage opposite in phase to said first source of voltage high-level periodic voltage and means commonly connecting said second source of high-level periodic voltage to all of said pairs of contact areas on said second monolithic body, a first source of high-level unidirectional voltage connected to all of said pairs of contact areas on said first monolithic body, and a second source of high-level unidirectional voltage, and means for connecting said second source of high-level unidirectional voltage to all of said pairs of contact areas on said second monolithic body.
Claim 17
Dependent Claim
151 words
An integrated circuit system for supplying sustaining voltages and discharge manipulating pulse voltages to one group of row conductors and one group of column conductors in a gas discharge device in which transversely oriented row and column conductors effecting discharges in the gas have dielectric charge-storage means, for charges produced on discharge, interposed between said row and column conductors and the gas, comprising in combination, at least a pair of monolithic semiconductor bodies, each processed to include a plurality of individual electrically isolated transistor switching circuits connected by conductors in circuit configurations described hereinafter including a plurality of contact areas to which connections to and from said circuit configurations are made, each said circuit configuration being functionally identical, wherein: each circuit configuration translates a low-level input pulse signal voltage to a high-level pulse signal voltage as said sustaining voltage, the output voltages from each circuit configuration being of opposite polarity, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-18 | 1975-04-19 | 1975-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-18 | 1979-04-19 | 1979-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-18 | 1983-04-19 | 1983-10-19 | $7700.00 | Window Closed / Lapsed |