Patent US3861968A successfully refreshed from Google Patents.
US3861968A
Expired / Lapsed
US
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Method of fabricating integrated circuit device structure with complementary elements utilizing selective thermal oxidation and selective epitaxial deposition
Assignee: International Business Machines Corp
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Filing: 1972-06-19
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Granted: 1975-01-21
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Expires: 1992-06-19
Abstract
Abstract A method of fabricating a planar dielectrically isolated semiconductor device by depositing a surface layer of dielectric material on a major surface of a monocrystalline substrate, removing portions of the layer to define annular channels, thermally oxidizing the exposed surface areas thereby forming annular ridges of SiO2, removing portions of the dielectric layer, selectively growing an epitaxial silicon layer over the surface wherein the surfaces of the annular ridges of SiO2 and the regions of epitaxial silicon are substantially co-planar. A semiconductor integrated circuit device having a silicon epitaxial layer on a monocrystalline substrate, a network of thermally oxidized silicon regions extending through the epitaxial layer, across the epitaxial layer-substrate interface and into the silicon substrate, the network separating the epitaxial silicon layer into individual pockets, a laterally extending region of low resistivity located generally at the epitaxial layer-substrate interface embodying a first conductivity type impurity, the first type impurity distribution in the epitaxial layer such that the concentration increases with depth.
Inventors
- 👤 Ingrid E Magdo
- 👤 Steven Magdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:27
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/67; H10D84/673; H10P; H10P14/00; H10P14/60; H10P14/61; H10W10/01; H10W10/011; H10W10/018; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/037; Y10S148/053; Y10S148/085; Y10S148/117
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
189 words
A METHOD FOR FABRICATING A PLANAR DIELECTRICALLY ISOLATED SEMICONDUCTOR STRUCTURE COMPRISING: PROVIDING A MONOCRYSTALLINE SILICON SUBSTRATE EMBODYING AN IMPURITY FOR SEMICONDUCTORS OF A FIRST TYPE, DEPOSITING A SURFACE LAYER OF DIELECTRIC MATERIAL ON A MAJOR SURFACE OF SAID SUBSTRATE, REMOVING PORTIONS OF SAID LAYER TO EXPOSE SURFACE AREA PORTIONS TO DEFINE ANNULAR CHANNELS, THERMALLY OXIDIZING THE EXPOSED SURFACE AREAS OF SAID SUBSTRATE THEREBY FORMING ANNULAR RIDGES OF SIO2 WHICH EXTEND TO A PREDETERMINED DISTANCE ABOVE AND BELOW THE SURFACE OF SAID SUBSTRATE, REMOVING PORTIONS OF SAID DIELECTRIC LAYER TO EXPOSE AT LEAST ADDITIONAL SURFACE AREAS OF SAID SUBSTRATE, DIFFUSING AN IMPURITY FOR SEMICONDUCTORS OF A SECOND OPPOSITE TYPE INTO SAID SILICON SUBSTRATE THROUGH THE EXPOSED SURFACE AREAS FORMING A HIGH CONDUCTIVITY REGION AND A GENERALLY LATERALLY EXTENDING P-N JUNCTION WITHIN SAID SUBSTRATE, SELECTIVELY GROWING AN EPITAXIAL SILICON LAYER OVER SAID ADDITIONAL SURFACE AREAS, SAID ANNULAR RIDGES OF SIO2 AND SAID LATERALLY EXTENDING P-N JUNCTION ELECTRICALLY ISOLATING POCKETS OF EPITAXIAL SILICON, THE SURFACES OF SAID RIDGES AND SAID REGIONS OF EPITAXIAL SILICON SUBSTANTIALLY CO-PLANAR. SELECTIVELY INTRODUCING IMPURITIES FOR SEMICONDUCTORS INTO SAID INSULATED POCKETS OF EPITAXIAL SILICON FORMING ACTIVE SEMICONDUCTOR DEVICES.
Claim 2
Independent Claim
189 words
A METHOD FOR FABRICATING A PLANAR DIELECTRICALLY ISOLATED SEMICONDUCTOR STRUCTURE COMPRISING: PROVIDING A MONOCRYSTALLINE SILICON SUBSTRATE EMBODYING AN IMPURITY FOR SEMICONDUCTORS OF A FIRST TYPE, DEPOSITING A SURFACE LAYER OF DIELECTRIC MATERIAL ON A MAJOR SURFACE OF SAID SUBSTRATE, REMOVING PORTIONS OF SAID LAYER TO EXPOSE SURFACE AREA PORTIONS TO DEFINE ANNULAR CHANNELS, THERMALLY OXIDIZING THE EXPOSED SURFACE AREAS OF SAID SUBSTRATE THEREBY FORMING ANNULAR RIDGES OF SIO2 WHICH EXTEND TO A PREDETERMINED DISTANCE ABOVE AND BELOW THE SURFACE OF SAID SUBSTRATE, REMOVING PORTIONS OF SAID DIELECTRIC LAYER TO EXPOSE AT LEAST ADDITIONAL SURFACE AREAS OF SAID SUBSTRATE, DIFFUSING AN IMPURITY FOR SEMICONDUCTORS OF A SECOND OPPOSITE TYPE INTO SAID SILICON SUBSTRATE THROUGH THE EXPOSED SURFACE AREAS FORMING A HIGH CONDUCTIVITY REGION AND A GENERALLY LATERALLY EXTENDING P-N JUNCTION WITHIN SAID SUBSTRATE, SELECTIVELY GROWING AN EPITAXIAL SILICON LAYER OVER SAID ADDITIONAL SURFACE AREAS, SAID ANNULAR RIDGES OF SIO2 AND SAID LATERALLY EXTENDING P-N JUNCTION ELECTRICALLY ISOLATING POCKETS OF EPITAXIAL SILICON, THE SURFACES OF SAID RIDGES AND SAID REGIONS OF EPITAXIAL SILICON SUBSTANTIALLY CO-PLANAR. SELECTIVELY INTRODUCING IMPURITIES FOR SEMICONDUCTORS INTO SAID INSULATED POCKETS OF EPITAXIAL SILICON FORMING ACTIVE SEMICONDUCTOR DEVICES.
Claim 3
Dependent Claim
14 words
The method of claim 1 wherein said layer of dielectric material is silicon nitride.
Claim 4
Dependent Claim
189 words
The method of claim 1 wherein there is fabricated in said structure at least one pair of complementary semiconductor devices comprising; subsequent to thermally oxidizing the annular channels of the exposed surface of the substrate, a portion of the surface layer of dielectric material is removed to expose only the first one of a pair of areas of surface layer portions surrounded by ridges of thermal SiO2, and the second type impurity for semiconductors is introduced into the substrate in the region exposed by the removal of the surface dielectric layer. forming a dIelectric layer over the exposed surface of the substrate, removing a portion of the surface layer of dielectric material to expose the second of a pair of areas of surface layer portions surrounded by ridges of thermal SiO2, introducing a first conductivity type impurity for semiconductors into the region exposed by the removal of the surface dielectric layer, removing the dielectric layer from the surface of the substrate, thermally oxidizing the surface of epitaxial layer subsequent to selective epitaxial silicon growth, and fabricating active devices of opposite type in the pair of resultant epitaxial silicon pockets.
Claim 5
Dependent Claim
191 words
The method of claim 1 wherein there is fabricated at least one pair of complementary semiconductor devices comprising; subsequent to thermally oxidizing the annular channels of the exposed surface of the substrate, the portions of the surface layer of dielectric material are removed to expose only a first one of a pair of areas of surface layer portions surrounded by thermal SiO2, and subsequent to introducing a second conductivity type impurity for semiconductors into the substrate in the region exposed by the removal of the surface dielectric layer, portions of the surface layer of dielectric material are removed to expose a second one of a pair of areas of surface layer portions surrounded by thermal SiO2, a first conductivity type impurity for semiconductors is embodied in said epitaxial silicon layer in a concentration sufficient to provide a first conductivity to the epitaxial layer over said second one of a pair of areas, but insufficient in the epitaxial layer over said first one of a pair of areas to overcome the impurity outdiffused from the high conductivity region, fabricating active devices of opposite type in said pair of resultant epitaxial silicon pockets.
Claim 6
Dependent Claim
171 words
The method of claim 1 wherein there is fabricated at least one pair of complementary semiconductor devices comprising; subsequent to thermally oxidizing the annular channels of the exposed surface of this substrate, portions of the surface layer of dielectric material are removed to expose both the first and second areas of a pair of areas of surface layer portions surrounded by ridges of thermal SiO2, introducing a second conductivity type impurity for semiconductors into the substrate in the regions exposed by the removal of the surface dielectric layer, forming a masking layer over the first one of a pair of areas of surface of the substrate, leaving exposed the second one of a pair of areas of surface layer portions surrounded by ridges of thermal SiO2, introducing a first opposite conductivity type impurity for semiconductors into the exposed area, removing the masking layer, and embodying a second opposite conductivity type dopant for semiconductors in said epitaxial layer, fabricating active devices of opposite type in the pair of resultant epitaxial silicon pockets.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-20 | 1978-07-22 | 1979-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-20 | 1982-07-22 | 1983-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-20 | 1986-07-22 | 1987-01-21 | $7700.00 | Window Closed / Lapsed |