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US3855536A
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Universal programmable logic function
Assignee: Westinghouse Electric Corp
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Filing: 1972-04-04
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Granted: 1974-12-17
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Expires: 1992-04-04
Abstract
Abstract A programmable, universal logic circuit is disclosed which provides with a minimum of back wiring, any of the basic logic functions 1/1, 1/2, 1/3, 1/4, 2/2, 2/3, 2/4, and reset (R-S) flip-flop and can be used as a basic building block in the construction of more complex logic functions than those presently described. The m/n notation completely describes most required functions in that n is the total number of inputs and m is the minimum number of those n inputs which must indicate a given logic state in order to cause some predetermined action. In addition, the universal circuit is designed such that unused inputs left floating, will be accepted as assuming an alternate logic state, not requiring some predetermined action. Thus, a m/n function can degenerate to a m/(n-1) or a m/(n-2) function if one or two inputs, respectively, are not supplied.
Inventors
- 👤 J Neuner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; G; G21; G21C; G21C17/00; Y; Y02; Y02E; Y02E30/00; Y02E30/30
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
187 words
A programmable, universal logic module comprising: logic means having a number of p input means where p is an integer greater than or equal to one, and a first output means, each of said input and output means capable of assuming either a first or second logical state, respectively, said logic means including a plurality of NAND gates, an AND gate having a plurality of inputs from the respective outputs of said NAND gates and an inverter having an input from said AND gate output and wherein the output of said inverter forms said first output means; n signal means, where n is an integer less than or equal to p, operably connected to n of said p input means, so as to provide at least one logical input signal to said logic means; and the remainder of said p minus n input means operably arranged so as to provide an output signal of said first state at said first output means whenever at least m of said n signal means assume said first state, where m is a predetermined integer less than or equal to n.
Claim 2
Dependent Claim
187 words
A programmable, universal logic module comprising: logic means having a number of p input means where p is an integer greater than or equal to one, and a first output means, each of said input and output means capable of assuming either a first or second logical state, respectively, said logic means including a plurality of NAND gates, an AND gate having a plurality of inputs from the respective outputs of said NAND gates and an inverter having an input from said AND gate output and wherein the output of said inverter forms said first output means; n signal means, where n is an integer less than or equal to p, operably connected to n of said p input means, so as to provide at least one logical input signal to said logic means; and the remainder of said p minus n input means operably arranged so as to provide an output signal of said first state at said first output means whenever at least m of said n signal means assume said first state, where m is a predetermined integer less than or equal to n.
Claim 3
Dependent Claim
43 words
The logic module of claim 1 including: programmable means for arranging said p minus n input means according to said predetermined integer m of said n signal means required to assume said first state before said first output means assumes said first state.
Claim 4
Dependent Claim
35 words
The logic module of claim 1 wherein said p input means and said first output means are constructed to be operably arranged to form a binary flip-flop without rearrangement or addition of internal logic components.
Claim 5
Dependent Claim
23 words
The logic module of claim 3 wherein said first output means is operably connected to at least one of said p input means.
Claim 6
Dependent Claim
16 words
The logic module of claim 4 wherein said n signal means are provided through ground connections.
Claim 7
Dependent Claim
84 words
The logic module of claim 5 wherein n equals 2, including: a first normally closed switch connected between ground and a first of said p input means and operably arranged to provide a reset signal to saId flip-flop when said first switch is opened; and a second normally open switch connected between ground and a second of said p input means and operably arranged to provide a set signal to said flip-flop when said second switch is closed and said first switch is open.
Claim 8
Dependent Claim
42 words
The logic module of claim 3 including: a noise filter operably connected to said first output means to filter pulses of relatively short duration due to noise so as to avoid changes in the state of said first output means caused thereby.
Claim 9
Dependent Claim
34 words
The logic module of claim 7 wherein said filter comprises: a resistor connected in series with said first output; and a capacitor connected at the output of said resistor, between said resistor and ground.
Claim 10
Dependent Claim
18 words
The logic module of claim 1 including: means for inhibiting said first output from assuming said first state.
Claim 11
Dependent Claim
72 words
The logic module of claim 9 wherein said inhibiting means comprises: a logic gate having a plurality of inputs, at least a first of said gate inputs being connected to said first output means; and inhibiting signal means connected to at least a second of said gate inputs, operable on command to provide a signal to said gate of a logical state sufficient to maintain said gate output at said second state.
Claim 12
Dependent Claim
23 words
The logic module of claim 1 wherein unconnected inputs to said logic means, left floating, will be accepted as assuming said second state.
Claim 13
Dependent Claim
51 words
The logic module of claim 1 wherein said logic means includes a second output positioned intermediate of said first output means and said NAND gates, operable to be connected to like second outputs on substantially similar logic modules to produce an AND''ed function of said modules at said first output means.
Claim 14
Dependent Claim
45 words
The logic module of claim 1 including: a plurality of substantially similar modules, each having a first output means, wherein the interconnection of said respective first output means provides an OR''ed function of said plurality of modules at each of said respective first output means.
Claim 15
Dependent Claim
25 words
The logic module of claim 1 wherein a plurality of said p input means are AND''ed to form a common input to said logic means.
Claim 16
Dependent Claim
73 words
The logic module of claim 1 wherein said inverter comprises a NAND gate having at least two inputs, the first of said inputs being connected to the output of said AND gate and the second of said inputs normally assuming said second state, operable upon command to provide a signal of said first state so as to inhibit the output of said NAND gate and maintain said NAND output at said second state.
Claim 17
Dependent Claim
171 words
The logic module of claim 1 wherein said logic means includes four NAND gates connected in parallel, each of said NAND gates having at least three inputs, said plurality of p input means comprising: a first terminal having parallel connections to a first input of a first, second and third of said four NAND gates, respectively; a second terminal having parallel connections to a second input on a first, second, and fourth of said four NAND gates, respectively; a third terminal; a fourth terminal; a second AND gate having inputs from said third and fourth terminals, respectively, and an output connected in parallel to a third input on said first NAND gate and a second input on said third and fourth NAND gates, respectively; a fifth terminal having parallel connections to a third input on said second, third and fourth NAND gates, respectively; a sixth terminal; a seventh terminal; and a diode connected between said sixth and seventh terminals, positioned to pass current from said seventh terminal to said sixth terminal.
Claim 18
Dependent Claim
55 words
The logic module of claim 16 wherein said fifth terminal is grounded and said signal means is operably coupled to said first terminal so as to provide an output signal of said first state at said first output means whenever said signal means provides an input signal of said first state to said first terMinal.
Claim 19
Dependent Claim
82 words
The logic module of claim 16 wherein said fifth terminal is grounded, a first of said n signal means is operably coupled to said first terminal and a second of said n signal means is operably coupled to said second terminal so as to provide an output signal of said first state at said first output means whenever at least either said first or second signal means provides an input signal of said first state to said first or second terminals, respectively.
Claim 20
Dependent Claim
98 words
The logic module of claim 16 wherein said fifth terminal is grounded, a first of said n signal means is operably coupled to said first terminal, a second of said n signal means is operably coupled to said second terminal and a third of said n signal means is operably coupled to said fourth terminal so as to provide an output signal of said first state at said first output means whenever at least either said first, second or third signal means provides an input signal of said first state to said first, second or fourth terminals, respectively.
Claim 21
Dependent Claim
123 words
The logic module of claim 16 wherein said fifth terminal is grounded, said third terminal is connected to said seventh terminal, a first of said n signal means is operably coupled to said first terminal a second of said n signal means is operably coupled to said second terminal, a third of said n signal means is operably coupled to said fourth terminal and a fourth of said n signal means is operably coupled to said sixth terminal so as to provide an output signal of said first state at said first output means whenever at least either said first, second, third or fourth signal means provides an input signal of said first state to said first, second, fourth or sixth terminals, respectively.
Claim 22
Dependent Claim
75 words
The logic module of claim 16 wherein a first of said n signal means is operably connected to said first terminal and a second of said n signal means is operably connected to said second terminal so as to provide an output signal of said first state at said first output means whenever both said first and second signal means provides an input signal of said first state to said first and second terminals, respectively.
Claim 23
Dependent Claim
93 words
The logic module of claim 16 wherein a first of said n signal means is operably connected to said first terminal, a second of said n signal means is operably connected to said second terminal and a third of said n signal means is operably connected to said fourth terminal so as to provide an output signal of said first state at said first output means whenever any two of said first, second or third signal means provides an input signal of said first state to said first, second or fourth terminals, respectively.
Claim 24
Dependent Claim
118 words
The logic module of claim 16 wherein said seventh terminal is connected to said fifth terminal, a first of said n signal means is operably connected to said first terminal, a second of said n signal means is operably connected to said second terminal, a third of said n signal means is operably connected to said fourth terminal and a fourth of said n signal means is operably connected to said sixth terminal so as to provide an output signal of said first state at said first output means whenever any two of said first, second, third or fourth signal means provides an input signal of said first state to said first, second, fourth or sixth terminals, respectively.
Claim 25
Dependent Claim
91 words
The logic module of claim 16 wherein said third terminal is connected to said first output, said fifth terminal is connected to said seventh terminal and said signal means comprises: a normally open switch connected between ground and said fourth terminal; a normally closed switch connected between ground and said sixth terminal; and said normally open and normally closed switches operating respectively as the set and reset switches of an R-S flip-flop providing a stable output of either said first or second state at said first output means, respectivEly, when switched.
Claim 26
Dependent Claim
96 words
The logic module of claim 1 wherein said logic means includes a first, second and third NAND gate connected, in parallel, each of said NAND gates having a first and second input, said plurality of p input means comprising: a first terminal having parallel connections to said first inputs on said first and second NAND gates, respectively; a second terminal having parallel connections to said second and first inputs on said first and third NAND gates respectively; and a third terminal having parallel connections to said second inputs on said second and third NAND gates, respectively.
Claim 27
Dependent Claim
60 words
The logic module of claim 25 wherein said third terminal is grounded and a first of said n signal means is operably connected to said second terminal so as to provide an output signal of said first state at said first output means whenever said first signal means provides an input signal of said first state to said second terminal.
Claim 28
Dependent Claim
83 words
The logic module of claim 25 wherein said third terminal is grounded, a first of said n signal means is operably connected to said second terminal and a second of said n signal means is operably connected to said first terminal so as to provide an output signal of said first state at said first output means whenever either said first signal means or said second signal means provides an input signal of said first state to said second or first terminals, respectively.
Claim 29
Dependent Claim
75 words
The logic module of claim 25 wherein a first of said n signal means is operably connected to said second terminal and a second of said n signal means is operably connected to said first terminal so as to provide an output signal of said first state at said first output means whenever both said first and second signal means provides an input signal of said first state to said second and first terminals, respectively.
Claim 30
Dependent Claim
93 words
The logic module of claim 25 wherein a first of said n signal means is operably connected to said second terminal, a second of said n signal means is operably connected to said first terminal and a third of said n signal means is operably connected to said third terminal so as to provide an output signal of said first state at said first output means whenever any two of said first, second or third signal means provides an input signal of said first state to said second, first or third terminals, respectively.
Claim 31
Dependent Claim
78 words
The logic module of claim 25 wherein said first terminal is connected to said first output terminal and said signal means comprises: a normally open switch connected between ground and said second terminal; a normally closed switch connected between ground and said third terminal; and said normally open and normally closed switches operating, respectively, as the set and reset switches of an R-S flip-flop, providing a stable output of either said first or second state, respectively, when switched.
Claim 32
Dependent Claim
22 words
The logic module of claim 1 wherein said first state is a logical zero and said second state is a logical one.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-16 | 1978-06-17 | 1978-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-16 | 1982-06-17 | 1982-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-16 | 1986-06-17 | 1986-12-17 | $7700.00 | Window Closed / Lapsed |