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US3793591A Expired / Lapsed US ⏱️ 0.0 years remaining

Pulse generator

Assignee: Bull HN Information Systems Italia SpA
•
Filing: 1972-07-13
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Granted: 1974-02-19
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Expires: 1992-07-13
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Abstract

Abstract A circuit is provided comprising of a minimum number of components which may operate as a pulse generator or a square wave generator by changing a single connection. The circuit includes an integrated circuit unit having a pair of NAND or NOR gates. A delay line has an input terminal connected to an output lead of one of the gates and an output terminal connected to one input lead of the other gate. A command signal is applied to one input lead of the first gate and to a second input lead of the other gate. The second input lead of the one gate is connected either to a suitable external voltage source for generating a single square pulse in response to a command signal or to the output terminal of the delay line for generating a succession of square pulses in response to the command signal. The circuit may also include a third gate having an output lead connected to the first input lead of the one gate, a first input lead connected to receive the command signal, and a second input lead connected to an output lead from the second gate, which output terminal serves as the output terminal of the circuit.

Inventors

  • 👤 C Trinca

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 11:16
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/06; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0307; H03K3/033

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 149 words
A circuit for generating at least one square pulse at a time in response to a command signal, comprising, in combination: an integrated circuital unit comprising at least a first and a second gate means, each said gate means being provided with at least a first and a second input lead and an output lead; an electromagnetic delay line having an input terminal connected to the output lead of said first gate means and at least an output terminal connected to a first input lead of said second gate means; impedance matching means connected to an output terminal of said delay line; an input terminal for receiving a command signal, connected to a first input lead of said first gate means and to a second input lead of said second gate means; and means for connecting said second input lead of said first gate means to a voltage source.
Claim 2
Dependent Claim 149 words
A circuit for generating at least one square pulse at a time in response to a command signal, comprising, in combination: an integrated circuital unit comprising at least a first and a second gate means, each said gate means being provided with at least a first and a second input lead and an output lead; an electromagnetic delay line having an input terminal connected to the output lead of said first gate means and at least an output terminal connected to a first input lead of said second gate means; impedance matching means connected to an output terminal of said delay line; an input terminal for receiving a command signal, connected to a first input lead of said first gate means and to a second input lead of said second gate means; and means for connecting said second input lead of said first gate means to a voltage source.
Claim 3
Dependent Claim 12 words
The circuit of claim 1, wherein said gate means are NAND gates.
Claim 4
Dependent Claim 12 words
The circuit of claim 1, wherein said gate means are NOR gates.
Claim 5
Dependent Claim 74 words
The circuit of claim 1, comprising, in addition, a third gate means, the output lead of said third gate means being connected to said first input lead of said first gate means, a first input lead of said third gate means being connected to an additional input terminal for receiving a command signal, and a second input lead of said third gate means being connected to the output lead of said second gate means.
Claim 6
Dependent Claim 30 words
The circuit of claim 1, wherein said voltage source comprises a suitable external voltage source, whereby said circuit will generate a single square pulse in response to said command signal.
Claim 7
Dependent Claim 34 words
The circuit of claim 1, wherein said voltage source comprises a suitable output terminal of said delay line, whereby said circuit will generate a succession of square pulses in response to said command signal.

References Cited (Backward Citations)

US3075089A Cited
US3283255A Cited
US3229119A Cited
US3219845A Cited
US3510787A Cited
US3571729A Cited
US3582674A Cited
US3660675A Cited
US3668423A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-02-18 1977-08-20 1978-02-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-02-18 1981-08-20 1982-02-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-02-18 1985-08-20 1986-02-19 $7700.00 Window Closed / Lapsed

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