Logic circuit delay system comprising monostable means for providing different time delays for positive and negative transitions

Claim 2

A logic circuit delay system comprising: an input and an output terminal, a D-type flip-flop circuit having signal and clock inputs and first and second complimentary outputs with the first output connected to said output terminal, a monostable circuit having an input and an output with the output connected to the clock input of said flip-flop circuit, said monostable circuit including an RC circuit establishing a time delay in which the monostable circuit remains in unstable state, logic means applying to the input of said monostable circuit a signal that is a function of the signals at said input and output terminals to thus clock said flip-flop and applying a function of the signal at the input terminal to the flip-flop input, and switching means operated by the logic signal at the second output of said flip-flop circuit for changing the effective value of the resistance in the RC circuit of said monostable circuit to thus alter the time constant of such circuit, whereby the logic signal at said output follows the logic signal at said input terminal with a different time delay for opposite logic signal transitions.

Claim 3

The system of claim 1 further defined by said RC circuit including a series connected first resistance and capacitance with the first resistance connected to a power supply terminal, and said switching means comprising a transistor controlled by the signal at the second flip-flop output terminal and connected between a power supply terminal and a second resistor in turn connected to the juncture of said capacitance and first resistance whereby conduction of said transistor effectively switches the resistance value in said RC circuit.

Claim 4

The system of claim 1 further defined by said logic means comprising a first NAND unit having the two inputs separately connected to said input and output terminals, an inverter connected between said input terminal and the flip-flop input, a second NAND unit having one input connected to thE output of said inverter and another input connected to the second output of said flip-flop circuit, and an AND unit having two inputs connected one to the output of each of said NAND units and an output connected to the input of said monostable circuit.

Claim 5

A logic circuit delay system comprising, an input terminal adapted to receive logic signals and an output terminal, one monostable circuit having a stable state with a first output signal and an unstable state with a second output signal and changing from stable to unstable state upon receipt of a logic transition from ''''one'''' to ''''zero,'''' said monostable circuit including a series RC circuit with a time constant establishing the time duration of the monostable circuit in the unstable state, a D-type integrated circuit flip-flop having an input, a clock input and first and second complimentary outputs, said clock input being connected to the output of said monostable circuit for operating the flip-flop upon receipt of a change from second to first outputs thereof, said first output being connected to said output terminal, logic circuitry applying a function of signals at said input terminal to the input of said flip-flop and applying a function of the signals at said input and output terminals to the input of said monostable circuit, and switching means operated by the signal at the second flip-flop output for connecting and disconnecting a second resistance in the RC circuit of said monostable circuit for varying the duration of second output signal from said monostable circuit whereby the logic signals at the output terminal follow logic signals at the input terminals at different time delays depending upon the direction of logic signal transition.

Claim 6

A logic circuit delay system comprising, an input terminal adapted to receive logic signals and an output terminal, one monostable circuit having a stable state with a first output signal and an unstable state with a second output signal and changing from stable to unstable state upon receipt of a logic transition from ''''one'''' to ''''zero,'''' said monostable circuit including a series RC circuit with a time constant establishing the time duration of the monostable circuit in the unstable state, a D-type integrated circuit flip-flop having an input, a clock input and first and second complimentary outputs, said clock input being connected to the output of said monostable circuit for operating the flip-flop upon receipt of a change from second to first outputs thereof, said first output being connected to said output terminal, logic circuitry applying a function of signals at said input terminal to the input of said flip-flop and applying a function of the signals at said input and output terminals to the input of said monostable circuit, and switching means operated by the signal at the second flip-flop output for connecting and disconnecting a second resistance in the RC circuit of said monostable circuit for varying the duration of second output signal from said monostable circuit whereby the logic signals at the output terminal follow logic signals at the input terminals at different time delays depending upon the direction of logic signal transition.